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| 19-5310; Rev 0; 7/10 TION KIT EVALUA BLE AILA AV Automotive, Two-Channel Proximity and Touch Sensor General Description Features S Low Average Operating Current (100A at 14V) S 1.2.fF LSB Capacitance-to-Digital Resolution (5pF MAX1441 The MAX1441 proximity and touch sensor IC is designed for capacitive proximity sensing in automotive passive remote keyless entry (PRKE) and other applications. This device provides signal processing to support two independent touch/proximity sensor channels. The device features two open-drain output pins with highvoltage capability up to 28V, as well as five digital I/Os to indicate sensing events. During manufacturing, JTAG programming uses four digital I/Os. The device uses grounded electrode capacitive sensing to measure capacitance between one of the two sense pins and the ground. A hand approaching a sense electrode attached to these sense pins causes a change in measured capacitance indicating the presence (touch or proximity) of the object. Activeguard outputs shield the sense electrode from unwanted sources without adding parasitic capacitance. Spread-spectrum techniques in the sensor excitation circuit reduce both electromagnetic emissions and susceptibility to interfering signals. In addition, the sensing excitation frequency is programmable from 100kHz to 500kHz in 10kHz steps to avoid interference. The sensor input signals are converted to a 12-bit digital data and are available to an on-chip microcontroller (FC). The device provides independent offset compensation of up to 63pF for each input channel. Each channel can be programmed to 5pF, 10pF, or 20pF full-scale range. The device features an internal MAXQ(R) microcontroller with 2kword of flash for user programs and 128 bytes of SRAM. This feature provides the ability to implement customized signal processing and discrimination algorithms that optimize performance in the systems. The device offers user-configurable general-purpose digital I/O lines. Power-on-reset (POR) circuitry provides consistent startup of the device, and a watchdog timer ensures long-term reliable operation of the user's software. The device is available in a 20-pin TSSOP package and is specified over the -40NC to +105NC automotive temperature range. Range) S 5V to 28V Operation S 45V Overvoltage Protection S Sinusoidal Excitation for Reduced EMI Emissions S Frequency Spreading Operation for Reduced EMI Susceptibility and Emissions S Active-Guard-Sense Architecture Provides Increased Flexibility in System Packaging S CMOS/LVCMOS-Compatible Outputs S Embedded C Supports User-Specified Adaptive Sense Algorithms S 2kwords Flash Memory S 128-Byte SRAM S 2kV ESD Immunity on Sensor I/O Lines S JTAG Serial Interface S Supports Two Independent Grounded Capacitor Sensor Inputs S -12V Reverse Voltage Protection with External Diode Applications PRKE System Proximity Sensing Object Detection Systems Ordering Information PART MAX1441GUP/V+ TEMP RANGE -40NC to +105NC PIN-PACKAGE 20 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. /V Denotes an automotive qualified part. MAXQ is a registered trademark of Maxim Integrated Products, Inc. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Automotive, Two-Channel Proximity and Touch Sensor MAX1441 ABSOLUTE MAXIMUM RATINGS (VDD = VAA, AGND = DGND, unless otherwise noted.) VBATT to AGND .....................................................-0.3V to +45V VAA, VDD to AGND..................................................-0.3V to +4V SINPUT1, SINPUT2, AGUD1, AGUD2 to AGND ...................................-0.3V to (VAA + 0.3V) RESET, P0._, I.C. to DGND ...................... -0.3V to (VDD + 0.3V) AGND to DGND ...................................................-0.3V to +0.3V OUT1, OUT2, to AGND .........................................-0.3V to +28V OUT_, P0._, Continuous Output Current ........................P 20mA Continuous Power Dissipation (TA = +70NC) Single-Layer PCB 20-Lead TSSOP (derate 11mW/NC above +70NC).......879mW Multilayer PCB 20-Lead TSSOP (derate 13.6mW/NC above +70NC)..1084mW Junction-to-Case Thermal Resistance (BJC) (Note 1) 20-Lead TSSOP ........................................................ +20NC/W Junction-to-Ambient Thermal Resistance (BJA) (Note 1) Single-Layer PCB 20-Lead TSSOP ........................................................ +91NC/W Multilayer PCB 20-Lead TSSOP ..................................................... +73.8NC/W Operating Temperature Range ........................ -40NC to +105NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VBATT = 5V to 28V, VAA = VDD, TA = -40NC to +105NC. Typical values are at VBATT = 14V, fEX = 300kHz, TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER Average Power-Supply Current CAPACITANCE-TO-DIGITAL CONVERTER Bit Resolution CRNG_[1:0] = 10 Input Capacitance Range CRNG_[1:0] = 01 CRNG_[1:0] = 00 Input Capacitance LSB Resolution Integral Nonlinearity Differential Nonlinearity Sampling Time Number of Effective Bits DC Input Current of SIN1, SIN2 INPUT CAPACITANCE EXCITATION SOURCE Source Peak-to-Peak Voltage Minimum Excitation Frequency Maximum Excitation Frequency fEXMIN fEXMAX 300kHz excitation frequency Frequency Control register = 0x0A (Note 3) Frequency Control register = 0x32 (Note 3) 0.96 1.0 100 500 1.21 VP-P kHz kHz INL DNL fEX = 300kHz (Note 3) 584 20pF capacitance range 10pF capacitance range 5pF capacitance range 12 20 10 5 4.8 2.4 1.2 1 0.5 600 11 300 624 %FS LSB Fs Bits nA fF pF Bits SYMBOL CONDITIONS 16ms capacitance-to-digital (C2D) conversion time, two active channels; CPU in sleep mode MIN TYP 100 MAX 120 UNITS FA 2 Automotive, Two-Channel Proximity and Touch Sensor ELECTRICAL CHARACTERISTICS (continued) (VBATT = 5V to 28V, VAA = VDD, TA = -40NC to +105NC. Typical values are at VBATT = 14V, fEX = 300kHz, TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER CAPACITIVE OFFSET DACS Offset Adjustment Range Offset Adjustment Resolution LOGIC INPUTS/OUTPUTS (P0._, RESET) Output Logic Low VOL Output Logic High Input Logic Low Input Logic High Leakage Current Port 0 Interrupt Minimum Pulse Width Output Logic Low Leakage Current MICROCONTROLLER Flash Program Memory Size Program Memory Clear Time Page Write Time Maximum Flash Erase/Write Cycles SRAM Size CPU Clock Frequency INTERNAL OSCILLATOR Oscillator Frequency VOLTAGE REGULATOR Input Voltage Maximum Dropout Voltage Quiescent Current Output Voltage VBATT VDROP IQ VAA 5V < VBATT < 28V, 0 < IAA < 10mA 3.2 IAA = 10mA 5 14 0.6 8 3.4 3.6 28 V V FA V Master oscillator RC oscillator 19.8 31.7 20.48 32 21.2 32.2 MHz kHz fCPU tCPM tW nCYC 16 bits wide 2k 38 10 100k 128 1.25 Words ms ms Cycles Bytes MHz VOL2 IL VOH VIL VIH IL ISINK = 2mA ISOURCE = 2mA 3.0V < VDD < 3.6V 3.0V < VDD < 3.6V I/O = high impedance 3.0V < VDD < 3.6V 2.4 0.01 20 1 VDD - 0.5 0.8 6 bits 63 1 0.4 pF pF V V V V FA ns SYMBOL CONDITIONS MIN TYP MAX UNITS MAX1441 HIGH-VOLTAGE OPEN-DRAIN OUTPUTS (OUT1, OUT2) ISINK = 2mA VOUT1 = VOUT2 = 25V 0.5 1 V FA Note 2: All units are production tested at TA = +25NC and TA = +105NC. Limits over the operating temperature range are guaranteed by design and characterization. Note 3: Measured indirectly by testing the excitation signal frequency. The excitation signal frequency is determined by the master oscillator frequency, which in turn determines the sample time. 3 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Typical Operating Characteristics (VBATT = 14V, VAA = VDD = 3.4V, TA = +25NC, unless otherwise noted.) CAPACITANCE ERROR vs. TEMPERATURE MAX1441 toc01 CAPACITANCE ERROR vs. PARALLEL RESISTANCE (SINPUT_ to AGUD_) MAX1441 toc02 CAPACITANCE ERROR vs. SERIES RESISTANCE CAPACITANCE ERROR (% FULL SCALE) 10pF RANGE, CO_ = 8, 15pF INPUT CAPACITANCE MAX1441 toc03 1.0 CAPACITANCE ERROR (% FULL SCALE) 0.8 0.6 0.4 0.2 0 -2.2 -0.4 -0.6 -0.8 -1.0 -50 CAPACITANCE ERROR (% FULL SCALE) CO_ = 0, 3.6pF INPUT CAPACITANCE 5pF RANGE 2 0 -2 -4 -6 -8 -10 10pF RANGE, CO_ = 8, 15pF INPUT CAPACITANCE 1.0 0.5 0 10pF RANGE 20pF RANGE -0.5 -25 0 25 50 75 100 125 10 100 1k 10k 100k -1.0 1 10 SERIES RESISTANCE (I) 100 TEMPERATURE (C) PARALLEL RESISTANCE (I) CAPACITANCE ERROR vs. POWER-SUPPLY VOLTAGE MAX1441 toc04 CAPACITANCE ERROR vs. EXCITATION FREQUENCY MAX1441 toc05 TOTAL SUPPLY CURRENT vs. CONVERSION PERIOD (ONE CHANNEL CONVERTING) 450 TOTAL SUPPLY CURRENT (A) 400 350 300 250 200 150 100 50 500 0 2 4 6 8 10 12 14 16 MAX1441 toc06 1.00 CAPACITANCE ERROR (% FULL SCALE) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 5 10 15 20 25 POWER-SUPPLY VOLTAGE (V) 5pF RANGE, CO_ = 0, 3.6pF INPUT CAPACITANCE 3 CAPACITANCE ERROR (% FULL SCALE) 20pF RANGE 2 1 0 -1 -2 -3 0 100 200 300 400 EXCITATION FREQUENCY (kHz) CO_ = 0, 3.6pF INPUT CAPACITANCE FOR 5pF RANGE, 7pF INPUT CAPACITANCE FOR 10pF RANGE, 14pF INPUT CAPACITANCE FOR 20pF RANGE 10pF RANGE 5pF RANGE 500 CPU IN STOP MODE CONVERSION PERIOD (ms) TOTAL SUPPLY CURRENT vs. CONVERSION PERIOD (TWO CHANNELS CONVERTING) MAX1441 toc07 LDO OUTPUT VOLTAGE vs. LOAD CURRENT MAX1441 toc08 LDO OUTPUT VOLTAGE vs. TEMPERATURE MAX1441 toc09 500 450 TOTAL SUPPLY CURRENT (A) 400 350 300 250 200 150 100 50 0 2 4 6 8 10 12 14 SSB2 = 0x01 CPU IN STOP MODE 3.40 3.385 3.380 3.375 3.39 VAA (V) VAA (V) VBATT = 14V VBATT = 28V VBATT = 5V VBATT = 5V 3.36 16 0 5 10 15 CONVERSION PERIOD (ms) LOAD CURRENT (mA) 3.360 3.355 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) 3.38 VBATT = 28V 3.37 VBATT = 14V 3.370 3.365 SSB2 = 0x1F 4 Automotive, Two-Channel Proximity and Touch Sensor Typical Operating Characteristics (continued) (VBATT = 14V, VAA = VDD = 3.4V, TA = +25NC, unless otherwise noted.) CAPACITANCE ERROR vs. EXCITATION BANDWIDTH (WITH IN-BAND INTERFERENCE) MAX1441 toc11 MAX1441 CAPACITANCE ERROR vs. INTERFERENCE FREQUENCY OFFSET CAPACITANCE ERROR (% FULL SCALE) 50 40 30 20 10 0 -10 100 150 200 250 300 350 400 450 500 INTERFERENCE FREQUENCY OFFSET (kHz) CAPACITANCE ERROR (% FULL SCALE) 10pF RANGE, CO_ = 8, 300kHz EXCITATION FREQUENCY, 500mVP-P INTERFERENCE FREQUENCY MAX1441 toc10 OUTPUT POWER vs. EXCITATION FREQUENCY SPECTRUM -10 -20 OUTPUT POWER (dBm) -30 -40 -50 -60 -70 -80 -90 -100 MAX1441 toc12 60 60 50 40 30 20 10 0 -10 0 50 100 150 10pF RANGE, CO_ = 8, 300kHz EXCITATION FREQUENCY, 300kHz, 500mVP-P INTERFERENCE FREQUENCY 0 200 0 200 400 600 800 1000 EXCITATION BANDWIDTH (kHz) EXCITATION FREQUENCY SPECTRUM (kHz) CAPACITANCE ERROR vs. EXCITATION BANDWIDTH MAX1441 toc13 DETECTION DISTANCE vs. ATxH REGISTER SETTING MAX1441 toc14 FULL-SCALE CAPACITANCE CHANGE vs. TEMPERATURE FULL-SCALE CAPACITANCE CHANGE (% FS) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -50 -25 0 25 50 75 100 125 MAX1441 toc15 0.5 CAPACITANCE ERROR (% FULL SCALE) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -10 10 30 50 70 90 5pF RANGE, CO_ = 0, 3.6pF INPUT CAPACITANCE 100 90 DETECTION DISTANCE (mm) 80 70 60 50 40 30 20 10 0 5pF RANGE 20pF RANGE 10pF RANGE 25cm x 2cm TOUCH PAD 3.0 20pF RANGE 10pF RANGE 5pF RANGE 110 130 150 0 5 10 15 20 25 30 35 EXCITATION BANDWIDTH (kHz) ATxH REGISTER SETTING TEMPERATURE (C) 5 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Pin Configuration TOP VIEW P0.4 1 P0.3/TMS 2 P0.2/INT2/TDI 3 P0.1/ INT1/ TDO 4 P0.0/ INT0 / TCK 5 RESET 6 AGUD1 7 SINPUT1 8 VAA 9 VBATT 10 20 VDD 19 DGND 18 OUT1 17 OUT2 16 I.C. MAX1441 15 I.C. 14 AGUD2 13 SINPUT2 12 AGND 11 N.C. TSSOP Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 16 17 18 19 20 NAME P0.4 P0.3/TMS P0.2/INT2/TDI P0.1/INT1/TDO P0.0/INT0/TCK RESET AGUD1 SINPUT1 VAA VBATT N.C. AGND SINPUT2 AGUD2 I.C. OUT2 OUT1 DGND VDD CPU Port 0 Bit 4. Digital input/output. CPU Port 0 Bit 3/TMS. Digital input/output. CPU Port 0 Bit 2/TDI. Digital input/output with configurable edge-triggered interrupt. CPU Port 0 Bit 1/TDO. Digital input/output with configurable edge-triggered interrupt. CPU Port 0 Bit 0/TCK. Digital input/output with configurable edge-triggered interrupt. Active-Low Reset Input. RESET requires an external pullup to VDD. Active Guard 1. Driven guard (active shield) output for channel 1. Sensor Input 1. Capacitive sensor electrode input for channel 1. Analog Power Supply. VAA is internally connected to the output of an on-chip 3.4V linear regulator. Connect VAA to VDD. Bypass VAA with a 0.47FF capacitor to AGND as close to VAA as possible. Power-Supply Voltage. Input to the 3.4V on-chip linear regulator. Bypass VBATT to AGND with a 0.1FF capacitor as close to VBATT as possible. No Connection. Not internally connected. Leave N.C. unconnected. Analog Ground. Connect AGND to DGND. Sensor Input 2. Capacitive sensor electrode input for channel 2. Active Guard 2. Driven guard (active shield) output for channel 2. Internally Connected. Leave unconnected. Open-Drain Output 2. CPU port 0 bit 6. Open-Drain Output 1. CPU port 0 bit 5. Digital Ground. Connect DGND to AGND. Digital Power Supply. Connect VDD to VAA. Bypass VDD with a 0.47FF capacitor to DGND as close to VDD as possible. FUNCTION 6 Automotive, Two-Channel Proximity and Touch Sensor Functional Diagram VBATT SINPUT1 MAX1441 C2D1 128 BYTE SRAM LDO VAA OFFSET COMP1 AGUD1 OUT1 COMMUNICATION AND MODE CONTROL DIGITAL CONTROL BLOCK OUT2 P0.0 PORT CONTROL P0.1 P0.2 P0.3 P0.4 SINUSOIDAL EXCITATION GENERATOR AGUD2 OFFSET COMP 2 SINPUT2 2-kword FLASH 2-kword ROM C2D2 MAXQ CORE CLOCK GENERATOR MAX1441 Typical Application Circuit PROGRAMMING PADS P0.4 P0.3/TMS P0.2/ INT2/TDI P0.1/ INT1/TDO P0.0/ INT0/TCK VBATT OUT1 VDD 10kI VDD 10kI VBATT OUT1 OUT2 SINPUT1 TOUCH PADS AGUD1 AGUD2 SINPUT2 MAX1441 OUT2 VAA VDD DGND AGND RESET 4.7kI 0.47F 0.47F 0.1F GND 7 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 t1 t2 t3 TCK t4 t5 TDI, TMS t6 t7 TDO Figure 1. JTAG Timing Diagram Detailed Description The MAX1441 is a 2-channel proximity and touch sensor that contains all the functions necessary to implement a proximity/touch detection system for vehicle PRKE systems and other applications. There are four principal architectural components to the device: the capacitive sensing analog front-end (AFE), a programmable CPU system, vehicle power, and I/O interface. Figure 1 shows the JTAG timing diagram. The AFE uses a 2-channel C2D converter to measure the capacitance present between sensor inputs SINPUT1 and SINPUT2 and the ambient ground (Figure 2). The AFE-sensing architecture converts approaching hand motion to 12-bit digital words that are operated by an algorithm in the CPU to ensure detection of positive events and minimizing false detections. The C2D converters can measure the input capacitance in three different ranges: 20pF, 10pF, and 5pF. Additionally, the C2Ds compensate up to 63pF of parasitic capacitance programmable in 1pF steps. In addition to capacitive proximity and touch detection, the AFE contains POR and a watchdog timer for monitoring CPU operations. The CPU runs the input capacitive data through an algorithm to ensure detection of positive events and minimizing false detections. The CPU system includes Flash-based program memory, SRAM, clocks, 8 and communications. The power input and signal outputs provide a complete interface to the vehicle power system and a robust communication signal to remote electronic control modules (ECUs). Each C2D converter produces an AC excitation voltage at inputs SINPUT1 and SINPUT2. The excitation voltage forces current through the capacitance connected to the sensor input. The current amplitude is proportional to the measured capacitance. The circuit measures the input capacitance by measuring the current flowing through the sensor inputs. This excitation signal is a sine wave with a frequency programmable from 100kHz to 500kHz in10kHz steps. The sinusoidal excitation allows for much lower EMI emissions compared to architectures that utilize simple square-wave excitation. The device drives the guard outputs AGUD1 and AUGD2 with the same signal from the sinusoidal excitation and shields the sense electrodes without adding parasitic capacitance. The converter measures the amplitude of the current and converts it to 12-bit digital data by a 12-bit C2D. The maximum conversion rate in each of the sensor channels is 1.66kHz. The microcontroller reads the input capacitance values and uses a user-supplied custom algorithm to detect the object proximity. Once the proximity is detected, Technical Function Automotive, Two-Channel Proximity and Touch Sensor MAX1441 SENSED OBJECT CURRENT FLOW INTO CAPACITANCE IC GROUND ELECTRIC FIELD SIGNAL MAX1441 EXCITATION: SINUSOIDAL VOLTAGE SOURCE Figure 2. Capacitive-Sensing Function the microcontroller can use the OUT1 or OUT2 pins to signal the event to external modules. The GPIOs can also provide system or configuration inputs to the microcontroller. The device has a power-saving standby mode for power-sensitive applications. In the standby mode, the microcontroller is powered down (CPU stop mode) and the analog front-end runs conversions at a reduced and programmable rate. A programmable hardware discriminator monitors the C2D converters outputs and brings the device out of standby mode when a potential object-proximity event is detected. The microcontroller can then analyze the capacitance data and validate the object-proximity event. The on-chip watchdog timer requires periodic servicing from the microcontroller to ensure proper and continuous operation. The watchdog timer resets the microcontroller if it is not serviced. This prevents the microcontroller from permanently hanging up due to unpredicted code behavior. The device features an on-chip voltage regulator allowing the part to operate with a wide range of power-supply voltage inputs: 5V to 28V with protection up to 45V. The regulator provides power for all the circuits making the device a very compact single-chip solution. The device's analog front-end is controlled by a number of control registers. The C2D conversion results and the AFE status are accessible through status and result registers. All AFE registers are available in the microcontroller data space. The control registers support read and write operations. The status and result registers are read-only registers. Communication between the CPU and the external interface and AFE registers is performed using read/write operations to CPU special-function registers (SFRs). The SFRs are organized in three sections (Section I-Section III); each section consists of six modules (M0-M5). Table 1 shows the location of each SFR within the SFR sections (see the Detailed Description for more details). The sensed capacitance range can be set independently for both channels. After power-up, the range is set to 20pF in both channels. Control Registers Sensed Capacitance Range 9 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 1. Important AFE Function Registers REGISTER CRNG FEL FEB CO1, CO2 SCT DSB SSB2 PD FUNCTION Adjust the capacitance range Set the frequency of excitation Set the bandwidth of the spreadspectrum modulation Set the capacitance offset Put the device in single-conversion mode Set the standby conversion rate Set the channel 2 standby conversion rate subdivider Put the AFE in power-down mode (does not affect CPU operation) Select the wakeup criteria (rate-ofchange and/or absolute capacitive change) Set the absolute wake-up threshold Set the capacitance rate-ofchange threshold Channel 1 conversion result Channel 2 conversion result Interrupt status of the AFE The C2D converter can be placed into a single conversion mode. In the single conversion mode, the microcontroller triggers a single conversion by setting bit SCT. If the single conversion mode is enabled, the analog front-end powers up only during the conversion. SCEN controls the single conversion mode. SCEN = 1 enables the single conversion mode and SCEN = 0 disables the single conversion mode. When single conversion mode is enabled, set bit SCT to trigger a conversion. SCT bit automatically clears after the conversion is completed. To save power, the analog front-end can be put in the standby state. During standby, the conversion rate is determined by the standby state conversion rate divider. SB controls the standby mode. SB = 1 enables the standby mode and SB = 0 disables the standby mode. There is only 1 SB bit common to both channels, so the channels cannot be placed in the standby state independently. The following sequence of control register writes to the PD register is recommended for entering standby mode: 1) Set PD to 06h to put both AFE channels into reset state. 2) Write DSB and SSB2 registers to set standby rate (if not already set). 3) Set PD to 00h to release AFE reset. 4) Set PD to 01h to enter standby mode. The maximum C2D conversion rate is 1.66kHz. Standby state uses conversion-rate reduction to save power. The conversion rate divider and conversion rate subdivider determine the final conversion rate. The DSB divider DSB[4:0] is common to both sensor channels. The conversion rate for channel 2 can be further reduced by the SSB2[4:0] divider. The conversion rate in kHz is determined by the equation: 1 fconv,channel1 = x 1.66kHz D fconv,channel2 = 1 x 1.66kHz DxS Single Conversion Mode Standby Control WU1, WU2 AT1H, AT2H RT1H, RT2H CRSLT1L, CRSLT1H CRSLT2L, CRSLT2H AFEINTST To avoid interference, the excitation frequency can be adjusted to automatically spread within a frequency range. The lower frequency bound and spread-spectrum bandwidth registers determine this range. Spread spectrum continuously changes the excitation frequency so that the radiated power is distributed over a frequency range rather than a single frequency. This lowers the radiated energy density and thus leads to a cleaner spectrum. In addition, by changing the excitation frequency, the capacitance measurement becomes more immune against interference signals. In case the capacitance measurement permanently reaches the upper or lower limit, there is a likelihood of a parasitic capacitance on top of the touch pads. This could be an ice coating on the door handle for example. In this case, the offset capacitance is adjusted so that the capacitance reenters the measurement range. A parasitic capacitance up to 63pF is compensated for each channel independently by properly setting the offset registers, CO1/CO2. 10 Excitation Frequency Standby State Conversion-Rate Divider Offset Capacitance where D is an integer number determined by a 5-bit word DSB[4:0] and S is an integer number determined by a 5-bit word SSB2[4:0]. The default value of D and S is one. D > 1 when SSB2 > 1. Automotive, Two-Channel Proximity and Touch Sensor Each sensor channel independently powers down through the PD register. Bit value 1 powers down the channel and bit value 0 powers up the channel. The excitation source circuitry powers down if both channels are powered down. Powering down both channels also resets all AFE internal circuits except for the AFE's control registers. The sensor wakes up when the measured capacitance exceeds a set capacitance threshold and/or a predefined rate of change in the capacitance. When an object approaches the sensor, the sensed capacitance starts changing. Once the capacitance value crosses the absolute value threshold and/or the capacitance rate of change crosses the rate-of-change threshold, the analog front-end is automatically put in the wake-up state and the SB bit is cleared. At the same time, the wake-up interrupt is sent to the microcontroller. The 8-bit word ATx[11:4] determines the absolute wake-up threshold and 8-bit word RTx[11:4] determines the rate-of-change threshold. Only the upper 8 bits are used in the threshold comparisons. Bit AOx determines if logical AND or OR operation is performed on the absolute and the rate-of-change threshold crossing events to produce the wake-up event. Bit value 1 sets the AND operation and bit value 0 sets OR operation. Both absolute and rateof-change threshold crossing detection can be enabled or disabled using bits AEx and REx. AEx bit value 1 enables absolute value detection and REx bit value 1 enables rate-of-change detection. The thresholds can be independently programmed in channels 1 and 2. The 12-bit result of the C2D conversion is available in CRSLT1L and CRSLT1H for channel 1 and in CRSLT2L Power-Down Control and CRSLT2H for channel 2. Bit OVRx is set to 1 if the current conversion caused overranging in the C2D converter. The interrupt status bit IDR1 is set to 1 when a new conversion result is available in channel 1. If the microcontroller does not read the conversion result before the next conversion is completed, the old conversion result is overwritten. The interrupt status bit IDR2 is set to 1 when a the new conversion result is available in channel 2. If the microcontroller does not read the conversion result before the next conversion is completed, the old conversion result is overwritten. The interrupt status bit IWUP1 is set to 1 when channel 1 detects a wake-up condition. The interrupt status bit IWUP2 is set to 1 when channel 2 detects a wake-up condition. MAX1441 Data Ready in Channel 1 Wake-Up Event Thresholds Data Ready in Channel 2 Wake-Up Event in Channel 1 Wake-Up Event in Channel 2 Detailed Controller Specification The device is based on the MAXQ RISC processor with Harvard memory architecture. Architecture Conversion Result Word The device implements all other standard MAXQ specialpurpose registers (SPRs). For details, see the SPR bit description in Table 5. Table 2 summarizes the SPRs and their address indexes. These registers can be accessed by user software. Specific MAXQ Special-Purpose Register Implementation Special-Purpose Registers Table 2. Special-Purpose Register Map MODULE AP A PFX IP SP DPC DP 01000 01001 01011 01100 01101 01110 01111 AP A0 PFX IP -- -- -- APC A1 -- -- SP -- -- -- A2 -- -- IV -- -- -- A3 -- -- -- Offs DP0 PSF -- -- -- -- DPC -- IC -- -- -- -- GR -- INDEX OF SPECIAL-PURPOSE REGISTER 01000 SC -- -- -- -- GRS -- 01001 01010 -- -- -- -- -- GRH -- -- -- -- -- -- GRXL -- 01011 IIR -- -- -- -- FP CP 01100 -- -- -- -- -- -- -- 01101 -- -- -- -- -- -- -- 01110 CKCN -- -- -- -- -- -- 01111 WDCN -- -- -- -- -- -- IMR -- -- -- LC0 GRL -- -- -- -- -- LC1 BP DP1 MODULE SPECIFIER 00000 00001 00010 00011 00100 00101 00110 00111 11 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Indexes not specified in this table are either reserved for hardware functional use or for future expansion; access to these locations has deterministic behavior that may not be the intention of the user. Register addresses highlighted in the table are reserved. Table 3 lists the SPR registers' functional bits and their bit positions. Table 4 specifies the default reset condition for all SPR bits. The default value for unused SPR bit locations is 0. For registers in the accumulator and Loop module, all 16 bits are undetermined after a reset. Undetermined values are labeled as "i" in the table. Special default values are labeled as "s" in the table. Table 5 details all SPRs and their bit description. Registers are also identified by their address in the form of (xxh, yyh), where xxh is the register index in hex and yyh is the module specifier in hex. Table 3. Special-Purpose Register Bit Function REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A0 A1 A2 A3 PFX IP SP IV LC0 LC1 DPC GR GRL GRS GRH GRXL DP0 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [7:0] [15:0] [7:0] [15:8] [7:0] [7:0] [15:8] [7:0] [15:0] MSB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LSB AP1 MOD1 C INS IM1 PWL -- -- AP0 MOD0 E IGE IM0 -- -- -- CLR Z -- IDS S -- -- -- -- -- GPF1 -- -- -- -- -- GPF0 -- -- -- -- -- OV -- -- IMS TAP IIS IDLE POR A0[15:0] A1[15:0] A2[15:0] A2[15:0] PFX[15:0] IP[15:0] SP[15:0] IV[15:0] LC0[15:0] LC1[15:0] -- ROD -- -- EWDI WD1 WD0 WDIF WTRF EWT RWT -- -- -- -- WBS0 -- -- GR[15:0] GRL[7:0] GR7 GR15 GRH[7:0] GR7 GR7 DP0[15:0] GR7 GR6 GR7 GR5 GR7 GR4 GR7 GR3 GR7 GR2 GR7 GR1 GR7 GR0 GR6 GR14 GR5 GR13 GR4 GR12 GR3 GR11 GR2 GR10 GR1 GR9 GR0 GR8 12 Automotive, Two-Channel Proximity and Touch Sensor Table 4. Special-Purpose Registers' Reset Values REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A0 A1 A2 A3 MSB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX1441 LSB 0000 0000 1000 0000 0000 1000 0000 1110 ss11 0000 0000 0000 0000 0000 0000 0000 0000 0000 00s0 0000 0000 0ss0 0000 0000 0000 0000 REGISTER PFX IP SP IV LC0 LC1 DPC GR GRL GRS GRH GRXL DP0 MSB 0000 1000 0000 0000 0000 0000 0000 0000 -- LSB 0000 0000 0000 0111 0000 0000 0000 0000 -- 0000 0000 0010 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1101 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- 0000 -- 0000 0000 0000 0000 Table 5. Special-Purpose Register Bit Description REGISTER AP (00h, 08h) Initialization Read/Write Access Accumulator Pointer (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Active Accumulator Select Bits [1:0]. The setting of these bits activates one of the four accumulators in the accumulator module (A) to function as the active accumulator for arithmetic and logical operations. The setting of these bits can be automatically incremented/decremented in a modulo fashion according to the setting to the APC register. Reserved. Read returns 0. Accumulator Pointer Control (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Modulo Bits [1:0]. The accumulator pointer autoincrement/decrement function is activated when these bits are set to a value other than 00b. The modulo is selected accordingly when active pointer autoincrement/decrement is active. APC[1:0]-MOD[1:0] MOD[1:0] 00 01 10 11 APC[5:2] APC.6-IDS Reserved. Read returns 0. Increment/Decrement Select. When this bit is cleared to 0, the content of AP increments after an arithmetic or logical operation. When this bit is set to 1, the content of AP is decremented after arithmetic or logical operation. AP Clear. When this bit is set to 1, the content of AP is cleared to 0. This bit automatically resets to 0 after clearing the AP register. Note if the MOVE APC, Acc instruction (980Ah) causes the CLR bit to set, the clear operation overrides other functions (i.e., the AP autoincrement/decrement does not happen). Modulo 2 Modulo 4 Reserved (modulo 4 if set) MODULO Default, no AP autoincrement/decrement DESCRIPTION AP[1:0] AP[7:2] APC (01h, 08h) Initialization Read/Write Access APC.7-CLR 13 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 5. Special-Purpose Register Bit Description (continued) REGISTER PSF (04h, 08h) Initialization Read/Write Access PSF.0-E DESCRIPTION Processor Status Flags Register (8-Bit Register) This register is set to 80h on all forms of reset. Unrestricted direct read. Write access to OV, E, C, GPF1, and GPF0 bits only. Equal Flag. This flag reflects the state of the Equal bit of a compare operation. It is 1 when the two values are equal. It is 0 when the two values are different. Writing a 1 to this bit by software is effectively set by the Equal flag. Carry Flag. This flag reflects the state of the Carry bit of the active accumulator. Its state may change after an arithmetic and logical operation. This flag is set to 1 if the last operation resulted in a carry/borrow. Otherwise, it is cleared to 0. Writing a 1 to this bit by software is effectively set by the Carry flag. Overflow Flag. This flag is set to 1 if there is a carry out of bit 14 but not out of bit 15, or a carry out of bit 15 bit not out of bit 14 from the last arithmetic operation; otherwise, the OV remains as 0. When adding signed numbers, OV indicates a negative number resulted as the sum of two positive operands, or a positive sum resulted from two negative operands. For subtraction, OV is set if a borrow is needed into bit 14 but not into bit 15, or into bit 15 but not into bit 14. This bit can be read and written by software to allow it to be restored after events such as interrupt servicing and debug operations. General-Purpose Flag 0. This is a general-purpose flag for software control. General-Purpose Flag 1. This is a general-purpose flag for software control. Reserved. Read returns 0. Sign Flag. This flag reflects the state of the Sign bit of the active accumulator (the most significant bit of the active accumulator). Its state may change after an arithmetic and logical operation or after the switch of the active accumulator. When it is set to 1, it indicates a negative value in the active accumulator from the last operation. When it is cleared to 0, it indicates a positive value. Zero Flag. This flag reflects the state of the Zero bit of the active accumulator (bit-wise NOR of the active accumulator). Its state may change after an arithmetic and logical operation or after the switch of the active accumulator. When it is set to 1, it indicates a zero value as a result of the last operation. When it is cleared to 0, it indicates a nonzero value. Interrupt and Control Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Interrupt Global Enable. The IGE bit enables the interrupt handler if set to 1. No interrupt to the CPU is allowed if this bit is cleared to 0. Interrupt In Service. The INS is set by the interrupt handler automatically when an interrupt is acknowledged. No further interrupt occurs as long as the INS remains set. The interrupt service routine can clear the INS to allow interrupt nesting. Otherwise, at the execution of an RETI/POPI instruction, the INS is cleared automatically by the interrupt handler. Reserved. Read returns 0. Interrupt Mask Register (8-Bit Register) This register is cleared 80h on all forms of reset. Unrestricted read. All bits have unrestricted write access, unless otherwise stated. Interrupt Mask 0. This bit is the module level interrupt enable for register module 0. To activate the interrupt request from module 0, the IGE and IM0 must be set and the INS is not set. Clearing this bit to 0 disables all interrupt sources in module 0. PSF.1-C PSF.2-OV PSF.3-GPF0 PSF.4-GPF1 PSF.5 PSF.6-S PSF.7-Z IC (05h, 08h) Initialization Read/Write Access IC.0-IGE IC.1-INS IC[7:2] IMR (06h, 08h) Initialization Read/Write Access IMR.0-IM0 14 Automotive, Two-Channel Proximity and Touch Sensor Table 5. Special-Purpose Register Bit Description (continued) REGISTER IMR.1-IM1 IMR[6:2] DESCRIPTION Interrupt Mask 1. This bit is the module level interrupt enable for register module 1. To activate the interrupt request from module 1, the IGE and IM1 must be set and the INS is not set. Clearing this bit to 0 disables all interrupt sources in module 1. Reserved. Read returns 0. Interrupt Mask 7. This bit is the module level interrupt enable for SPR modules. To activate the interrupt request from any SPR modules, the IGE and IMS must be set and the INS is not set. Clearing this bit to 0 disables all interrupt sources in all SPR modules. This bit is read only and defaults to 1 on all forms of reset. System Control Register (8-Bit Register) This register is set to 82h on POR and set to 1000 00s0b on all other forms of reset. Unrestricted read. See the following bit definition for write restriction. Reserved. Read returns 0. Password Lock. This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte password to be matched with the password in the program space before allowing access to the ROM loader's utilities for read/write of program memory and debug functions. ROM Operation Done. This bit is used to signify completion of a ROM operation sequence to the control units. This allows the debug engine to determine the status of a ROM sequence. Setting this bit to logic 1 causes an internal system reset if the SPE bit is also set. Setting the ROD bit clears the SPE bit if it is set and the ROD bit is automatically cleared by hardware once the control unit acknowledges the done indication. Setting this bit to 1 causes either an internal system reset or the debug engine to execute a command to clear this bit. Either way, the applicable code is never able to read a 1 from this bit. Reserved. Read returns 0. Test Access (JTAG) Port Enable. This bit controls whether the test access port special function pins are enabled. The TAP defaults to being enabled. Clearing this bit to 0 disables the TAP special function on the JTAG pins. Interrupt Identification Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted direct read. Write access is a no operation. Interrupt ID 0. When this bit is set to 1, it indicates that there is at least one pending interrupt in module 0. This bit is set only if the interrupt flag and its corresponding enable bit are set. The II0 is cleared by hardware when the interrupt source is disabled or the flag is cleared by software. Interrupt ID 1. When this bit is set to 1, it indicates that there is at least one pending interrupt in module 1. This bit is set only if the interrupt flag and its corresponding enable bit are set. The II1 is cleared by hardware when the interrupt source is disabled or the flag is cleared by software. Reserved. Read returns 0. Interrupt ID System. When this bit is set to 1, it indicates that there is at least one pending interrupt in SPR modules. This bit is set only if the interrupt flag and its corresponding enable bit is set. The IIS is cleared by hardware when the interrupt source is disabled or the flag is cleared by software. System Clock Control Register (8-Bit Register) This register is set to 060h on all forms of resets. Unrestricted read. See the following bit description for write restriction. MAX1441 IMR.7-IMS SC (08h, 08h) Initialization Read/Write Access SC.0 SC.1-PWL SC.2-ROD SC[6:3] SC.7-TAP IIR (0Bh, 08h) Initialization Read/Write Access IIR.0-II0 IIR.1-II1 IIR[6:2] IIR.7-IIS CKCN (0Eh, 08h) Initialization Read/Write Access 15 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 5. Special-Purpose Register Bit Description (continued) REGISTER CKCN[3:0] CKCN.4-STOP CKCN[6:5] CKCN.7-IDLE WDCN (0Fh, 08h) Initialization Read/Write Access WDCN.0-RWT DESCRIPTION Reserved. These bits are read only. Read returns 0. Stop Mode Select. Setting this bit to 1 stops program execution and commences low-power CPU operation. This bit is cleared by a reset or any of the enabled external interrupts. Setting and resetting the STOP bit does not change the system clock source and its divide ratio. Reserved. These bits are read only. Read returns 11b. IDLE Mode Select. Setting this bit to a 1 stops program execution by halting the instruction pointer and disabling the internal module selects (similar to a NOP operation). This provides a low-power mode that does not require a system warm-up on exit. Watchdog Timer Control (8-Bit Register) This register is set to B2h on POR and set to ss00 0ss0b on all other forms of reset. Unrestricted read. Unrestricted write access, unless stated otherwise. Reset Watchdog Timer. Setting this bit resets the watchdog timer count. This bit must be set before the watchdog timer expires, or a watchdog timer reset and/or interrupt is generated if enabled. The timeout period is defined by WD1 and WD0. This bit is always 0 when read. Enable Watchdog Timer Reset. Setting this bit to 1 enables the watchdog timer to reset the device; clearing this bit to 0 disables the watchdog timer reset. It has no effect on the timer itself and its ability to generate a watchdog interrupt. This bit is set to 1 following a power-on reset and is unaffected by all other resets. This bit can only be written once by software. Once written, the value of this bit is not altered by any subsequent write. Watchdog Timer Reset Flag. When set, this bit indicates that a watchdog timer reset has occurred. It is typically interrogated to determine if a reset was caused by the watchdog timer. It is cleared by power-on reset, but otherwise must be cleared by software before the next reset of any kind to allow software to work correctly. Setting this bit by software does not generate a watchdog timer reset. If the EWT bit is cleared, the watchdog timer has no effect on this bit. Watchdog Interrupt Flag. This bit is set to 1 by a watchdog timeout, which indicates a watchdog timer event has occurred if EWT and/or EWDI are set. When the WDIF is set, EWT and EWDI determine the action to take. Setting this bit from 0 to 1 also activates the reset counter for the watchdog reset timeout, which allows 512 clock cycles for the system to reset the watchdog timer using the RWT bit. Setting this bit in software generates a watchdog interrupt if enabled and triggers the reset counter. This bit must be cleared in software before exiting the interrupt service routine, or another interrupt is generated. The reset counter must be cleared by RWT once started. EWT WDCN.3-WDIF x 0 0 1 1 EWDI x 0 1 0 1 WDIF 0 x 1 1 1 No interrupt has occurred. Watchdog disable, clock is gated off. Watchdog interrupt has occurred. No interrupt has been generated. Watchdog reset occurs in 512 clock cycles if RWT is not set or WDIF not cleared. Watchdog interrupt has occurred. Watchdog reset occurs in 512 clock cycles if RWT is not set or WDIF not cleared. ACTIONS WDCN.1-EWT WDCN.2-WTRF Note: Software cannot set this flag. Software can only clear this flag. This restriction is specific to the MAX1441 only and does not apply to other MAXQ products. 16 Automotive, Two-Channel Proximity and Touch Sensor Table 5. Special-Purpose Register Bit Description (continued) REGISTER DESCRIPTION Watchdog Timer Mode Select Bits [1:0]. These bits are used to provide a user selection of watchdog timer interrupt periods, which determine the watchdog timer interrupt timeout when the watchdog timer is enabled. All watchdog timer reset timeouts follow the programmed interrupt timeouts by 512 times the clock divide ratio oscillator cycles. Mode select bit settings and the timeout values. Changing the WD1:0 bit settings resets the watchdog timer unless the 512 clock reset counter has already started, in which case, changing the WD1:0 bits does not affect the watchdog timer or reset counter. These bits can only be written when simultaneously resetting the timer (RWT = 1). Otherwise, a write to these control bits is ignored (i.e., user software sets the RWT bit and changes the WD value in the same instruction). Watchdog Interrupt Enable. Setting this bit to 1 enables interrupt requests generated by the watchdog timer. Clearing this bit to 0 disables the interrupt requests. This bit is cleared following a power-on reset and unaffected by all other resets. Power-On Reset Flag. This bit indicates whether the last reset was a power-on reset. This bit is typically interrogated following a reset. It must be cleared before the next reset of any kind for software to work correctly. This bit is set following a power-on reset and unaffected by all other resets. Accumulator 0 (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Accumulator 0 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. Otherwise, it can be used as general-purpose working register. Accumulator 1 (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Accumulator 1 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. Otherwise, it can be used as a general-purpose working register. Accumulator 2 (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Accumulator 2 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. Otherwise, it can be used as a general-purpose working register. Accumulator 3 (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Accumulator 3 Bits [15:0]. This register serves as the accumulator for arithmetic and logical operation when activated by the accumulator pointer. Otherwise, it can be used as a general-purpose working register. MAX1441 WDCN[5:4]-WD[1:0] WDCN.6-EWDI WDCN.7-POR A0 (00h, 09h) Initialization Read/Write Access A0[15:0] A1 (01h, 09h) Initialization Read/Write Access A1[15:0] A2 (02h, 09h) Initialization Read/Write Access A2[15:0] A3 (03h, 09h) Initialization Read/Write Access A3[15:0] 17 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 5. Special-Purpose Register Bit Description (continued) REGISTER PFX (00h-07h, 0Bh) Initialization Read/Write Access Prefix Register (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Prefix Register Bits [7:0]. This register provides a means to supply the high-order byte of data to a 16-bit destination register with 8-bit sources. To transfer 8-bit source data to a 16-bit destination, the high-order byte must first transfer to the PFX register. This activates the PFX for the next instruction cycle, which concatenates PFX data with the source operand to form a 16-bit data for the target destination. The PFX holds data for only one cycle before resetting all its bits to 0. When PFX is used as a source, it basically transfers a zero value to the destination when PFX has not been activated in the preceding instruction. Prefix Register Bits [15:8]. Reserved. Read returns 0. Note: Subdecodes (1h-7h) function as extension bits for source/destination indexing. Instruction Pointer (16-Bit Register) This register is set to 8000h on all forms of reset. Unrestricted read/write. Instruction Pointer Bits [15:0]. This register contains the next program address to be fetched by the fetch unit. The content of IP is automatically incremented by 1 after each fetch. New data written to this register causes the program flow to branch to the new location. Read access to the IP register does not affect the program flow. Stack Pointer (16-Bit Register) This register is cleared to 002Fh on all forms of reset. Unrestricted read/write. Stack Pointer Bits [5:0]. The SP designates the memory location that is at the top of the stack, which is the storage location of the last word. The contents of the SP is postdecremented for a POP operation, and is preincremented for a PUSH operation. Reserved. Read returns 0. Interrupt Vector Register (16-Bit Register) This register is set to 07FDh on all forms of reset. Unrestricted read only. Interrupt Vector Bits [15:0]. This register contains the interrupt vector address. The interrupt handler forces a hardware call to this vector location when there is an enabled interrupt request pending. Loop Counter 0 (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Loop Counter 0 Bits [15:0]. This register contains the loop count for a loop operation. The content of LC0 is automatically decremented by 1 after each loop. This register is normally used as a loop control for conditional branch to a new location. Loop Counter 1 (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Loop Counter 1 Bits [15:0]. This register contains the loop count for a loop operation. The content of LC1 is automatically decremented by 1 after each loop. This register is normally used as loop control for conditional branch to a new location. DESCRIPTION PFX[7:0] PFX[15:8] IP (00h, 0Ch) Initialization Read/Write Access IP[15:0] SP (01h, 0Dh) Initialization Read/Write Access SP[5:0] SP[15:6] IV (02h, 0Dh) Initialization Read/Write Access IV[15:0] LC0 (06h, 0Dh) Initialization Read/Write Access LC0[15:0] LC1 (07h, 0Dh) Initialization Read/Write Access LC1[15:0] 18 Automotive, Two-Channel Proximity and Touch Sensor Table 5. Special-Purpose Register Bit Description (continued) REGISTER DPC (04h, 0Eh) Initialization Read/Write Access DPC[1:0]-SDPS[1:0] DPC.2-WBS0 DPC[15:3] GR (05h, 0Eh) Initialization Read/Write Access DESCRIPTION Data Pointer Control Register (16-Bit Register) This register is set to 0004h on all forms of reset. Unrestricted read/write. Reserved. Read returns 0. Word/Byte Select 0. This bit selects access mode for DP[0]. When WBS0 is set to logic 1, the DP[0] is operated in word mode for data-memory access; when WBS0 is cleared to logic 0, DP[0] is operated in byte mode for data-memory access. Reserved. Read returns 0. General Register (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. General Register Bits [15:0]. This register is intended primarily for supporting byte operation on 16-bit data. GR can be used as a 16-bit general-purpose register and allows byte-readable and byte-writable operations through the corresponding GRL and GRH register locations. It also supports byte-swap operation when read through the GRS register location. General Register Low Byte (8-Bit Location) This register is cleared to 00h on all forms of reset. Unrestricted read/write. General Register Low Byte Bits [7:0]. This register location reflects the low byte of the GR register and is intended primarily for supporting byte operation on 16-bit data. Any data written to this location stores in the low byte of the GR register, and a read in this location returns the least significant data byte of the GR register. General Register Byte Swap (16-Bit Location) This register is cleared to 0000h on all forms of reset. Unrestricted read only. General Register Byte Swap Bits [15:0]. This read-only register location reflects the byte-swapped data of the GR register and is intended primarily for supporting byte operation on 16-bit data. Reading this register location returns the byte-swapped data from the GR register. General Register High Byte (8-Bit Location) This register is cleared to 00h on all forms of reset. Unrestricted read/write. General Register High Byte Bits [7:0]. This register location reflects the high byte of the GR register and is intended primarily for supporting byte operation on 16-bit data. Any data written to this location stores in the high byte of the GR register, and read this location returns the most significant data byte of the GR register. General Register Sign Extended Low Byte (16-Bit Location) This register is cleared to 0000h on all forms of reset. Unrestricted read only. General Register Sign Extended Byte Bits [15:0]. This read-only register location reflects the sign extended low byte of the GR register. When read, the upper 8 bits contain the logic value of bit 7 of the GR register, and the lower 8 bits are the low byte of the GR register. MAX1441 GR[15:0] GRL (06h, 0Eh) Initialization Read/Write Access GRL[7:0] GRS (08h, 0Eh) Initialization Read/Write Access GRS[15:0] GRH (09h, 0Eh) Initialization Read/Write Access GRH[7:0] GRXL (0Ah, 0Eh) Initialization Read/Write Access GRXL[15:0] 19 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 5. Special-Purpose Register Bit Description (continued) REGISTER DP0 (03h, 0Fh) Initialization Read/Write Access DP0[15:0] Data Pointer 0 (16-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. Data Pointer 0 Bits [15:0]. This register contains the data address for data memory access. The contents of DP0 can be automatically incremented/decremented for read/write data-memory operation. DESCRIPTION All peripherals and operations that are not explicit instructions in the device are controlled using specialfunction registers (SFRs). These registers allow communication and data exchange between the CPU and the peripherals. Normally, interaction between a peripheral Special-Function Registers and the processor is initiated through the interrupt handler. SFRs can be 8-bit or 16-bit registers and most of the SFRs are accessible by user software (Tables 6, 7, 8). All undefined or unallocated registers should be treated as reserved registers. Table 6. Special-Function Register Map Section I MODULE M[x] M0 M1 M2 M3 M4 M5 SPECIFIER 00000 00001 00010 00011 00100 00101 00000 PO0 AFEINTST -- -- -- -- INDEX OF SPECIAL-FUNCTION REGISTER (SECTION I) 00001 EIF0 SCT -- -- -- -- 00010 EIE0 CRNG -- -- -- -- 00011 EIES0 PD -- -- -- -- 00100 TCON WU1 -- -- -- -- 00101 TFRQ WU2 -- -- -- -- 00110 TCNT FEL -- -- -- -- 00111 -- FEB -- -- -- -- Table 7. Special-Function Register Map Section II MODULE M[x] M0 M1 M2 M3 M4 M5 SPECIFIER 00000 00001 00010 00011 00100 00101 01000 PI0 CRSLT1L -- -- -- -- INDEX OF SPECIAL-FUNCTION REGISTER (SECTION II) 01001 PD0 CRSLT1H -- -- -- -- 01010 -- CRSLT2L -- -- -- -- 01011 -- CRSLT2H -- -- -- -- 01100 TM2 AT1H -- -- -- -- 01101 -- RT1H -- -- -- -- 01110 -- AT2H -- -- -- -- 01111 BRKP RT2H -- -- -- -- Table 8. Special-Function Register Map (Section III) MODULE M0 M1 M2 M3 M4 M5 00000 00001 00010 00011 00100 00101 -- CO1 -- -- -- -- -- CO2 -- -- -- -- -- DSB -- -- -- -- -- -- -- -- -- INDEX OF SPECIAL-FUNCTION REGISTER (SECTION III) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LOCK ICDT0 ICDT1 ICDC ICDF ICDB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ICDA -- -- -- -- -- ICDD -- -- -- -- -- -- -- -- -- -- -- M[x] SPECIFIER 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 SSB2 AFEIE 20 Automotive, Two-Channel Proximity and Touch Sensor Table 9 lists the SFR register's functional bits and their bit positions. Table 10 specifies the default reset condition for all SFR bits. Special default values are labeled as "s" in the table. The default value for unused SFR bit locations is 0. Table 11 details all SFRs and their bit description. Registers are also identified by their address in the form of (xxh, yyh), where xxh is the register index in hex and yyh is the module specifier in hex. MAX1441 Table 9. Special-Function Register Bit Function REGISTER MODULE 0 PO0 [7:0] EIF0 [7:0] EIE0 [7:0] EIES0 [7:0] TCON [7:0] TFRQ [7:0] TCNT [7:0] PI0 [7:0] PD0 [7:0] BRKP [15:0] ICDT0 [15:0] ICDT1 [15:0] ICDC [7:0] ICDF [7:0] ICDB [7:0] ICDA [15:0] ICDD [15:0] MODULE 1 AFEINTST [7:0] SCT [7:0] CRNG PD WU1 WU2 FEL FEB CRSLT1L CRSLT1H CRSLT2L CRSLT2H AT1H RT1H AT2H RT2H CO1 CO2 DSB SSB2 AFEIE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] MSB -- -- -- -- TMRIE PO0[6:0] -- -- -- -- -- -- TMREN TCLK TFRQ[7:0] TCNT[7:0] -- -- -- -- -- -- ICDT0[15:0] ICDT1[15:0] -- CMD3 -- PSS1 -- -- ICDA[15:0] ICDD[15:0] -- -- -- -- -- -- IWUP2 -- -- -- -- -- LSB -- -- -- TMRIF -- -- -- TVALID IE[2:0] EX[2:0] IT[2:0] TPSS[2:0] -- -- -- PI0[6:0] PD0[6:0] -- -- -- -- -- -- -- -- -- -- -- -- BREAK DME -- ICDB[7:0] -- -- -- -- -- -- CMD2 PSS0 -- CMD1 JSPE -- CMD0 TXC -- -- -- -- -- -- -- -- -- CRSLT1[3:0] CRSLT1[11:4] CRSLT2[3:0] CRSLT2[11:4] -- -- -- -- -- -- -- -- -- -- -- -- -- -- CRNG2 [1:0] -- -- -- -- -- -- -- -- IWUP1 -- -- PD2 AO1 AO2 IDR2 SCEN CRNG1 [1:0] PD1 RE1 RE2 IDR1 SCT SB AE1 AE2 -- -- -- -- AT1[11:4] RT1[11:4] AT2[11:4] RT2[11:4] FEL[5:0] FEB[4:0] -- -- -- -- -- -- -- -- -- -- -- -- OVR1 -- OVR2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CO1[5:0] CO2[5:0] DSB[4:0] SSB2[4:0] EIWUP2 EIWUP1 EDR2 EDR1 21 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 10. Special-Function Register Reset Values MODULE 0 REGISTER PO0 EIF0 EIE0 EIES0 TCON TFRQ TCNT PI0 PD0 BRKPNT ICDT0 ICDT1 ICDC ICDF ICDB ICDA ICDD -- -- -- -- MSB -- -- -- -- -- -- -- -- -- 0000 0000 0000 -- -- -- 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 -- -- -- 0000 0000 -- -- -- -- LSB 0111 0000 0000 0000 0000 0000 0000 ssss 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- 1111 0000 0000 0000 0000 0000 0000 ssss 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- REGISTER AFEINTST SCT CRNG PD WU1 WU2 FEL FEB CRSLT1L CRSLT1H CRSLT2L CRSLT2H AT1H RT1H AT2H RT2H CO1 CO2 DSB SSB2 AFEIE MODULE 1 MSB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- LSB 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0010 0000 0100 0100 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0000 Table 11. Special-Function Register Bit Description REGISTER PO0 (00h, 00h) Initialization Read/Write Access Port 0 Output Register (8-Bit Register) This register is set to 7Fh on all forms of reset. Unrestricted read/write. Port 0 Output Register Bits [6:0]. This register stores output data for this port when it is defined as an output port. Reading from the register returns the contents of the register and does not necessarily reflect the true state of the port pins. Changing the direction of this port does not change the data contents of the register. Reserved. Read returns 0. External Interrupt Flag 0 Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Interrupt Edge Detect Bits [2:0]. These bits are set when the edge selected by ITx is detected on the interrupt pin, INTx. Setting any of the bits to 1 generates an interrupt to the CPU if the corresponding interrupt is enabled. These bits remain set until cleared by software or a reset. It must be cleared by software before exiting the interrupt source routine or another interrupt is generated as long as the bit remains set. Reserved. Read returns 0. DESCRIPTION PO0[6:0] PO0.7 EIF0 (01h, 00h) Initialization Read/Write Access EIF0[2:0]-IE[2:0] EIF0[7:3] 22 Automotive, Two-Channel Proximity and Touch Sensor Table 11. Special-Function Register Bit Description (continued) REGISTER EIE0 (02h, 00h) Initialization Read/Write Access EIE0[2:0]-EX[2:0] EIE0[7:3] EIES0 (03h, 00h) Initialization Read/Write Access EIES0[2:0]-IT[2:0] EIF0[7:3] TCON (04h, 00h) Initialization Read/Write Access DESCRIPTION External Interrupt Enable 0 Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Enable External Interrupt Bits [2:0]. Setting any of these bits to 1 enables the corresponding external interrupt, INTx. Clearing any of the bits to 0 disables the corresponding interrupt function. Reserved. Read returns 0. External Interrupt Edge Select 0 Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Edge Select for External Interrupt Bits [2:0]: ITx = 0 - External Interrupt INTx is positive edge triggered. ITx = 1 - External Interrupt INTx is negative edge triggered. Reserved. Read returns 0. Timer Control Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read. Write is unrestricted, unless otherwise stated in the following bit description. Timer Prescaler Select Bits [2:0]. The following bits select the prescaler value that apply to the select source clock. TPSS[2:0] 000 001 TCON[2:0]-TPSS[2:0] 010 011 100 101 110 111 These bits can only be written to when the timer is disabled (TMREN = 0). TCON.3-TCLK Timer Clock Select. This bit selects the clock source used by the Timer. When this bit is cleared to 0, the system clock is used as the clock source. When this bit is set to 1, the 32kHz is used. This bit can only be written to when the timer is disabled (TMREN = 0). Timer Enable. Setting this bit to 1 enables the Timer. Clearing this bit halts the Timer. The Timer continues to run in Stop mode if TMREN = 1. Timer Value Valid. This bit indicates whether TCNT returns the valid value when 32kHz is selected as the clock source. When this bit is set to 1, TCNT returns the valid value. When this bit is cleared to 0, TCNT returns 0000h. This bit has no meaning when the system clock is used as a clock source. In this case, TCNT always returns valid value. Timer Interrupt Flag. This bit is set to 1 when the Timer count matches the timer frequency value. It is cleared either by software or a reset. A 0 on this bit indicates no Timer overflow has been detected. Timer Interrupt Enable. Setting this bit to 1 enables the Timer interrupt. Clearing this bit to 0 disables the Timer interrupt. PRESCALE VALUE /1 /4 /16 /64 /256 /512 /1024 /2048 MAX1441 TCON.4-TMREN TCON.5-TVALID TCON.6-TMRIF TCON.7-TMRIE 23 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 11. Special-Function Register Bit Description (continued) REGISTER TFRQ (05h, 00h) Initialization Read/Write Access TFRQ[7:0] TCNT (06h, 00h) Initialization Read/Write Access TCNT[7:0] PI0 (08h, 00h) Initialization Read/Write Access PI0[6:0] PI0.7 PD0 (09h, 00h) Initialization Read/Write Access Timer Frequency Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read. This register can only be written when TCLK = 0; otherwise, a write to this register is ignored. Timer Reload Register Bits [7:0]. This register is used to store Timer overflow value. Timer Count Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read. This register can only be written when TCLK = 0; otherwise, a write to this register is ignored. Timer Count Register Bits [7:0]. This register is used to load and read a value to/from the Timer. Port 0 Input Register (8-Bit Register) The reset value for this register is dependent on the logical states of the pins. Unrestricted read only Port 0 Input Register Bits [6:0]. This register reflects the logic state of its port pins when read. Reserved. Read returns 0. Port 0 Direction Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Port 0 Direction Register Bits [6:0]. This register is used to determine the direction of the Port 0 function. The port pins are independently controlled by their direction bits. When a bit is set to 1, its corresponding pin is used as an output; data in the PO register is driven on the pin. When a bit is cleared to 0, its corresponding pin is used as an input, and allows an external signal to drive the pin. Note that when functioning as an input, the port pin is driven to a high-impedance state. Reserved. Read returns 0. Software Breakpoint Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. BREAK. Setting this bit causes an emulation breakpoint to activate and halt the system on the instruction, which sets the bit. This bit is connected directly to the SBPE input on the emulation block and is self-clearing. A read of this bit always returns zero. Reserved. Read returns 0. In-Circuit Debug Temp 0 Register (16-Bit Register) This register is cleared to 0000h after a power-on reset or a Test-Logic-Reset TAP state. Unrestricted read/write access by the CPU from background, debug, or test (TME = 1) mode. In-Circuit Debug Temp 0 Register Bits [15:0]. This register is intended for use by the utility ROM in-circuit debug or test routines as temporary storage to save registers that might otherwise have to be placed in the stack (e.g., DPC, DP[n]). In-Circuit Debug Temp 1 Register (16-Bit Register) This register is cleared to 0000h after a power-on reset or a Test-Logic-Reset TAP state. Unrestricted read/write access by the CPU from background, debug, or test (TME = 1) mode. In-Circuit Debug Temp 1 Register Bits [15:0]. This register is intended for use by the utility ROM in-circuit debug or test routines as temporary storage to save registers that might otherwise have to be placed in the stack (e.g., DPC, DP[n]). DESCRIPTION PD0[6:0] PD0.7 BRKP (0Fh, 00h) Initialization Read/Write Access BRKP.0-BREAK BRKP[7:1] ICDT0 (18h, 00h) Initialization Read/Write Access ICDT0[15:0] ICDT1 (19h, 00h) Initialization Read/Write Access ICDT1[15:0] 24 Automotive, Two-Channel Proximity and Touch Sensor Table 11. Special-Function Register Bit Description (continued) REGISTER ICDC (1Ah, 00h) Initialization Read/Write Access DESCRIPTION In-Circuit Debug Control Register (8-Bit Register) This register is cleared to 00h after a power-on reset or a Test-Logic-Reset TAP state. Unrestricted read; all bits are set and cleared by the debug engine only. This register can be accessed using a valid JTAG debug engine command. Command Bits [3:0]. These bits reflect the current host command in debug mode. These bits are set by the debug engine and allow the ROM code to determine the course of action. CMD[3:0] 0000 0001 0010 0011 ICDC[3:0]-CMD[3:0] 0100 0101 0110 0111 1000 1001 1010 Other ICDC.4 ICDC.5-REGE ICDC.6-TE No operation Read register Read data memory Read stack memory Write register Write data memory Trace, single step the CPU Return, return to background mode Unlock password Read selected register Execute Test Execute Test (only supported when TME = 1) Reserved ACTION MAX1441 Reserved. Read returns 0. Break-On Register Enable. This bit always returns 0. Therefore, BP4 and BP5 breakpoints are not supported. Timer Enabled. This bit always returns 0 and the timer is automatically disabled in debug mode. Debug Mode Enable. When this bit is cleared to 0, background mode commands can be executed but breakpoints are disabled. When this bit is set to 1, breakpoints are enabled while background mode commands can still be entered. This bit is only set or cleared from background mode. This bit has no meaning for the ROM code. In-Circuit Debug Flag Register (8-Bit Register) This register is cleared to 00h after a power-on reset or a Test-Logic-Reset TAP state. Unrestricted read; only bit 0 is writable by the CPU. Serial Transfer Complete. This bit is set by the hardware at the end of a transfer cycle at the TAP communication link. The TXC helps the debug engine to recognize host requests, either command or data. This bit is normally set by ROM code to signify/request sending or receiving data; the TXC must be cleared by the debug engine once set. CPU writes to the TXC bit result in clearing the JTAG PSS1:0 bits. System Program Enable. The SPE bit used for in-system programming support and its logical state, when read by the CPU, always reflects the logical-OR of the SPE bit and the SPE bit of the System Programming Buffer (SPB) register in the TAP module (which is accessible using JTAG). The logical state of this bit determines the program flow after a reset. When it is set to logic 1, in-system programming is executed by the utility ROM. When it is cleared to 0, execution is transferred to user code. This bit allows read access by the CPU and is cleared to 0 only on a power-on reset or Test-Logic-Reset. The JTAG SPE bit is cleared by hardware when the ROD bit is set. The SPE bit is read only. 25 ICDC.7-DME ICDF (1Bh, 00h) Initialization Read/Write Access ICDF.0-TXC ICDF.1-SPE Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 11. Special-Function Register Bit Description (continued) REGISTER ICDF[7:2] ICDB (1Ch, 00h) Initialization Read/Write Access Reserved. Read returns 0. In-Circuit Debug Buffer Register (8-Bit Register) This register is cleared to 00h after a power-on reset or a Test-Logic-Reset TAP state. Unrestricted read/write by CPU. In-Circuit Debug Buffer Bits [7:0]. ICDB serves as the parallel holding buffer for the debug shift register of the TAP. Data is read from or written to ICDB for serial communication between the debug function and the external host. This register is mapped to the SFR space for read/write access by the CPU. In-Circuit Debug Address Register (16-Bit Register) This register is cleared to FFFFh after a power-on reset or a Test-Logic-Reset TAP state. Unrestricted read by the CPU. This register can be accessed using a valid JTAG debug engine command. In-Circuit Debug Address Bits [15:0]. This register serves as the address register for the debug engine to store a specific location for the ROM code execution. This register is also used by the debug engine as a mask register to mask out don't care bits in the ICDD register when BP5 is used as a register breakpoint. When a bit in this register is set to 1, the corresponding bit location in the ICDD register is compared to the updating destination data to determine if a break should be generated. When a bit in this register is cleared, the corresponding bit in the ICDD register becomes a don't care and is not compared against the updating data. When all bits in this register are cleared, any updated data pattern causes a break when the BP5 register matches the destination register address of the current instruction. In-Circuit Debug Data Register (16-Bit Register) This register is cleared to 0000h after a power-on reset or a Test-Logic-Reset TAP state. Unrestricted read by the CPU. This register can be accessed using a valid JTAG debug engine command. In-Circuit Debug Data Bits [15:0]. This register serves as the data/count register for the debug engine to store data or read count for ROM code execution. This register is also used by the debug engine as a data register for content matching when BP5 is used as a register breakpoint. In this case, only data bits in this register with their corresponding mask bits in the ICDA register set is compared with the updated destination data to determine if a break should be generated. AFE Interrupt Status Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. See the following individual bit definitions for write restriction. CH1 Data Ready Interrupt Flag. This bit is set to 1 when a new conversion result is available. This bit remains set unless cleared by software. CH2 Data Ready Interrupt Flag. This bit is set to 1 when a new conversion result is available. This bit remains set unless cleared by software. CH1 Wake-Up Event Interrupt Flag. This bit is set to 1 when a wake-up condition is detected. This bit remains set unless cleared by software. CH2 Wake-Up Event Interrupt Flag. This bit is set to 1 when a wake-up condition is detected. This bit remains set unless cleared by software. Reserved. Read returns 0. DESCRIPTION ICDB[7:0] ICDA (1Dh, 00h) Initialization Read/Write Access ICDA[15:0] ICDD (1Eh, 00h) Initialization Read/Write Access ICDD[15:0] AFEINTST (00h, 01h) Initialization Read/Write Access AFEINTST.0-IDR1 AFEINTST.1-IDR2 AFEINTST.2-IWUP1 AFEINTST.3-IWUP2 AFEINTST[7:4] 26 Automotive, Two-Channel Proximity and Touch Sensor Table 11. Special-Function Register Bit Description (continued) REGISTER SCT (01h, 01h) Initialization Read/Write Access SCT.0-SCT DESCRIPTION Single Conversion Register (8-Bit Register) This register is cleared to 02h on all forms of reset. Unrestricted read/write. See the following individual bit definitions for write restriction. Single Conversion Trigger. Setting this bit to 1 initiates a conversion to an enabled channel (PDx = 0) when the single conversion mode is enabled. Once set to 1, a write to this bit is ignored. This bit is automatically cleared to 0 at the end of the conversion. Single Conversion Enable. Setting this bit to 1 enables the single conversion mode. Clearing this bit to 0 disables the single conversion mode. Reserved. Read returns 0. Input Range Register (8-Bit Register) This register is cleared to 22h on all forms of reset. Unrestricted read/write. CH1 Capacitance Input Range Bits [1:0]. These bits set the capacitance input range. CRNG1[1:0] CRNG[1:0]- CRNG1[1:0] 00 01 10 11 CRNG[3:2] Reserved. Read returns 0. CH2 Capacitance Input Range Bits [1:0]. These bits set the capacitance input range. CRNG2[1:0] CRNG[5:4]- CRNG2[1:0] 00 01 10 11 CRNG[7:6] PD (03h, 01h) Initialization Read/Write Access Reserved. Read returns 0. Power-Down Register (8-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read. Write to this register is unrestricted, unless otherwise stated in the following bit definition. Standby Enable. Setting this bit to 1 enables the standby mode for both channels. Clearing this bit to 0 disables the standby mode. When standby mode is enabled, the conversion occurs at a divided-down rate as defined by DSB and SSB. Once set, this bit can be cleared by software. This bit is automatically cleared to 0 if a wake-up event occurs. CH1 Power-Down. Setting this bit to 1 powers down CH1. Clearing this bit to 0 powers up CH1. CH2 Power-Down. Setting this bit to 1 powers down CH2. Clearing this bit to 0 powers up CH2. Reserved. Read returns 0. CH1 Wake-Up Control Register (8-Bit Register) This register is cleared to 04h on all forms of reset. Unrestricted read/write. CH1 Absolute Wake-Up Threshold Enable. Setting this bit to 1 enables the absolute wake-up threshold detection. Clearing this bit to 0 disables the absolute wake-up threshold detection. CAPACITANCE RANGE (pF) 5 10 20 20 CAPACITANCE RANGE (pF) 5 10 20 20 MAX1441 SCT.1-SCEN SCT[7:2] CRNG (02h, 01h) Initialization Read/Write Access PD.0-SB PD.1-PD1 PD.2-PD2 PD[7:3] WU1 (04h, 01h) Initialization Read/Write Access WU1.0-AE1 27 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 11. Special-Function Register Bit Description (continued) REGISTER WU1.1-RE1 DESCRIPTION CH1 Rate-of-Change Wake-Up Threshold Enable. Setting this bit to 1 enables the rate-of-change wake-up threshold detection. Clearing this bit to 0 disables the rate-of-change wake-up threshold detection. CH1 AND/OR Mode Enable. Setting this bit to 1 causes an interrupt to the CPU when both the absolute and rate-of-change threshold are exceeded. Both AEI and REI must be enabled when AO1 is set to 1. Clearing this bit to 0 causes an interrupt to the CPU when either the absolute threshold or rate-of-change threshold is exceeded. Reserved. Read returns 0. Channel 2 Wake-Up Control Register (8-Bit Register) This register is cleared to 04h on all forms of reset. Unrestricted read/write. CH2 Absolute Wake-Up Threshold Enable. Setting this bit to 1 enables the absolute wake-up threshold detection. Clearing this bit to 0 disables the absolute wake-up threshold detection. CH2 Rate-of-Change Wake-Up Threshold Enable. Setting this bit to 1 enables the rate-of-change wake-up threshold detection. Clearing this bit to 0 disables the rate-of-change wake-up threshold detection. CH2 AND/OR Mode Enable. Setting this bit to 1 causes an interrupt to the CPU when both the absolute and rate-of-change threshold are exceeded. Clearing this bit to 0 causes an interrupt to the CPU when either the absolute or rate-of-change threshold is exceeded. Reserved. Read returns 0. Excitation Frequency Low-Limit Register (8-Bit Register) This register is set to 1Eh on all forms of reset. Unrestricted read/write. Excitation Frequency Low-Limit Bits [5:0]. These bits set the lower end of the excitation frequency (FEL x 10kHz). Reserved. Read returns 0. Excitation Frequency Spread-Spectrum Bandwidth Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Excitation Frequency Spread-Spectrum Bandwidth Bits [4:0]. These bits set the excitation frequency bandwidth (FEB x 20kHz). Reserved. Read returns 0. Channel 1 Conversion Result Register (8-Bit Register) This register is cleared to 00h on all forms of reset. This register is read only. CH1 Overrange Flag. The overrange flag is set to 1 by hardware if the current conversion causes overranging of the C-to-D conversion. This bit is cleared to 0 if the current conversion does not cause overranging. Reserved. Read returns 0. Channel 1 Conversion Result Bits[3:0]. This register contains the lower 4 bits of the C-to-D conversion. WU1.2-AO1 WU1[7:3] WU2 (05h, 01h) Initialization Read/Write Access WU2.0-AE2 WU2.1-RE2 WU2.2-AO2 WU2[7:3] FEL (06h, 01h) Initialization Read/Write Access FEL[5:0] FEL[7:6] FEB (07h, 01h) Initialization Read/Write Access FEB[4:0] FEB[7:5] CRSLT1L (08h, 01h) Initialization Read/Write Access CRSLT1L.0-OVR1 CRSLT1L[3:1] CRSLT1L[7:4] 28 Automotive, Two-Channel Proximity and Touch Sensor Table 11. Special-Function Register Bit Description (continued) REGISTER CRSLT1H (09h, 01h) Initialization Read/Write Access CRSLT1H[7:0] CRSLT2L (0Ah, 01h) Initialization Read/Write Access CRSLT2L.0-OVR2 CRSLT2L[3:0] CRSLT2L[7:4] CRSLT2H (0Bh, 01h) Initialization Read/Write Access CRSLT2H[7:0] AT1H (0Ch, 01h) Initialization Read/Write Access AT1H[7:0] RT1H (0Dh, 01h) Initialization Read/Write Access RT1H[7:0] AT2H (0Eh, 01h) Initialization Read/Write Access AT2H[7:0] RT2H (0Fh, 01h) Initialization Read/Write Access RT2H[7:0] DESCRIPTION Channel 1 Conversion Result Register (8-Bit Register) This register is cleared to 00h on all forms of reset. This register is read-only. Channel 1 Conversion Result Bits[11:4]. This register contains the upper 8 bits of the C-to-D conversion. Channel 2 Conversion Result Register (8-Bit Register) This register is cleared to 00h on all forms of reset. This register is read-only. CH2 Overrange Flag. The overrange flag is set to 1 by hardware if the current conversion causes overranging of the C-to-D conversion. This bit is cleared to 0 if the current conversion does not cause overranging. Reserved. Read returns 0. Channel 2 Conversion Result Bits [3:0]. This register contains the lower 4 bits of the C-to-D conversion. Channel 2 Conversion Result Register (8-Bit Register) This register is cleared to 00h on all forms of reset. This register is read only. Channel 2 Conversion Result Bits [11:4]. This register contains the upper 8 bits of the C-to-D conversion. CH1 Absolute Wake-Up Threshold Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. CH1 Absolute Wake-Up Threshold Bits [11:4]. This register contains the threshold value against which a wake-up event is generated in standby mode. This register has no effect if the absolute threshold is not enabled. CH1 Rate-of-Change Wake-Up Threshold Register (8-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. CH1 Rate-of-Change Wake-Up Threshold Bits [11:4]. This register contains the threshold value against which a wake-up event is generated in standby mode. This register has no effect if the rate-of-change threshold is not enabled. CH2 Absolute Wake-Up Threshold Register (8-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. CH2 Absolute Wake-Up Threshold Bits [11:4]. This register contains the threshold value against which a wake-up event is generated in standby mode. This register has no effect if the absolute threshold is not enabled. CH2 Rate-of-Change Wake-Up Threshold Register (8-Bit Register) This register is cleared to 0000h on all forms of reset. Unrestricted read/write. CH2 Rate-of-Change Wake-Up Threshold Bits [11:4]. This register contains the threshold value against which a wake-up event is generated in standby mode. This register has no effect if the rate-of-change threshold is not enabled. 29 MAX1441 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 11. Special-Function Register Bit Description (continued) REGISTER CO1 (10h, 01h) Initialization Read/Write Access CO1[5:0] CO1[7:6] CO2 (11h, 01h) Initialization Read/Write Access CO2[5:0] CO2[7:6] DSB (12h, 01h) Initialization Read/Write Access DSB[4:0] DSB[7:5] SSB2 (13h, 01h) Initialization Read/Write Access SSB2[4:0] SSB2[7:5] AFEIE (14h, 01h) Initialization Read/Write Access AFEIE.0-EDR1 AFEIE.1-EDR2 AFEIE.2-EIWUP1 AFEIE.3-EIWUP2 AFEIE[7:4] DESCRIPTION Channel 1 Capacitance Offset Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Channel 1 Capacitance Offset Bits [5:0]. These bits select the amount of capacitance compensation to be applied. Capacitance can be adjusted in a 1pF increment up to 63pF. Reserved. Read returns 0. Channel 2 Capacitance Offset Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. Channel 2 Capacitance Offset Bits [5:0]. These bits select the amount of capacitance compensation to be applied. Capacitance can be adjusted in a 1pF increment up to 63pF. Reserved. Read returns 0. Standby State Conversion Rate Divider Register (8-Bit Register) This register is cleared to 01h on all forms of reset. Unrestricted read/write. Standby State Conversion Rate Divider Bits [4:0]. These bits set the conversion rate divider for both channels 1 and 2 in the standby state. The conversion rate is reduced by DSB[4:0]. Reserved. Read returns 0. Channel 2 Standby State Conversion Rate Subdivider Register (8-Bit Register) This register is cleared to 01h on all forms of reset. Unrestricted read/write. Channel 2 Standby State Conversion Rate Divider Bits [4:0]. These bits set the additional channel 2 conversion rate divider that is applied, in addition to the DSB divide ratio in the standby state. The conversion rate for channel 2 is divided by DSB[4:0] x SSB2[4:0]. Reserved. Read returns 0. AFE Interrupt Enable Register (8-Bit Register) This register is cleared to 00h on all forms of reset. Unrestricted read/write. CH1 Data Ready Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when the IDR1 bit is set to 1. Clearing this bit to 0 disables an interrupt from generating. CH2 Data Ready Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when the IDR2 bit is set to 1. Clearing this bit to 0 disables an interrupt from generating. CH1 Wake-Up Event Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when EIWUP1 = 1. Clearing this bit to 0 disables an interrupt from generating. CH2 Wake-Up Event Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU when EIWUP2 = 1. Clearing this bit to 0 disables an interrupt from generating. Reserved. Read returns 0. 30 Automotive, Two-Channel Proximity and Touch Sensor Memory Organization There are three distinct memory areas in the IC's registers, program memory, and data memory. All memories are located on-chip. Data memory is realized by SRAM memory, which allows both read and write access; program memory is implemented with nonvolatile Flash memory. The user application codes are programmed using a bootstrap loader. The bootstrap loader program is located in the utility code space. From a user perspective, the utility code segment is a program segment in the program memory map. As illustrated in Figure 3, the device incorporates 4KB program memory, 4KB Utility ROM, and 128 bytes SRAM data memory. Data memory is contiguous from 0000h to 03Fh words. Programmable memory begins at address 0000h and is contiguous through a maximum of 7FFh words. The device also incorporates a soft stack using data RAM for the stack. The MMU provides access controls for program and data memories. The built-in bootstrap loader is used to support Flash memory erase/program operations. Two of the register modules (M0/M1) are used by the device. On-chip data memory begins at address 0000h and is contiguous through the internal data memory space to 03Fh words (128 bytes). Data memory mapping and access control are handled by the MMU. Read/write access to the data memory can be in word or in byte. The program memory is implemented using nonvolatile Flash memory. Flash memory provides in-system programming capability but this memory technology requires erase operation before a write operation and the time required to carry out write access is extremely long. Write access to nonvolatile memory is actually performed by utility ROM code for the device. MAX1441 Register Space Data Memory Program Memory FFFFh WBSn = 1 FFFFh WBSn = 0 FFFFh PROGRAM SPACE REGISTERS FFh 87FFh 2K x 16 UTILITY CODE 8000h 1Fh 0Fh DATA SPACE SPRs 07h 06h 07FFh SFRs 00h 0000h 2K x 16 PROGRAM MEMORY 003Fh 64 x 16 DATA RAM 007Fh 0000h 0000h Figure 3. Memory Map 31 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Utility Code A program segment on top of the 32K program memory space is realized by ROM, which provides system utility functions: * Resetvector * Bootstrapfunctionforsysteminitialization * In-circuitdebug Reset vector is located in the utility code, starting at 8000h. Following each reset, the processor automatically starts execution from the utility code, allowing the utility code to perform any necessary system-support functions. Note that the default value for the instruction pointer is effectively set to the lowest address of the program memory; a reset forces the program address to 8000h directly and activates the utility code for code fetch. The most significant bit of the address bus continues to be held high until the program flow is first progressed outside the utility code memory range. The SPE bit can be used to force the processor to bypass the utility code reset routine and start execution from the user code after a reset. The device is always reset to 8000h after a reset. If the SPE bit is cleared to logic 0, the processor vectors out of the utility code segment immediately and starts standard user-program execution at location 0000h of the program memory. However, if the SPE bit is set to logic 1, the processor starts execution from the utility code, entering to the bootstrap loader mode. The SPE bit is defaulted to 0. To enter the bootstrap loader mode, the SPE bit can be set during POR using the JTAG interface. The bootstrap loader should clear the SPE bit to 0 after program initialization. If the utility code is bypassed during reset, the initialization vector should be stored in the lower bytes of the program memory. Nonvolatile Memory Programming The program memory is realized in the Flash memory, which provides a storage area for critical code/data that must be maintained in case of power-down. Write access to the nonvolatile memory is performed by a utility code routine that is initiated by a user call to the subroutine. The ROM routine can perform the write to the Flash. The device supports only a software stack that is located in the normal data memory space and its contents are fixed as 16-bit words. The program stack supports subroutine calls and system interrupts. The stack can also be 32 used to store variables by the user software. The program stack is addressed by the stack pointer (SP). The SP designates the stack location at the top of the stack, which is the location of the last word stored. The SP register is a 16-bit register but only the lower bits are implemented as per C_SP_LEN configuration. The SP is defaulted to 02F0h and the content of the SP is predecremented for write and postincremented for read. The SP value is automatically decreased before a write operation, and automatically increased after a read operation. Note that the PUSH and POP instructions are provided for the convenience of programmers who prefer to use these traditional stack-related instructions. From the assembly and the hardware point of view, the PUSH and POP instructions are equivalent to the MOVE @++SP, XXX and MOVE XXX, @SP-- instruction, respectively. These MOVE instructions involved with indirect SP predecrement/ postincrement the SP register value accordingly. Memory allocation and access control for program and data memories are managed by the MMU. Program stack is controlled by a dedicated state machine for fast stack operation. Memory Management Unit The instruction pointer is fully decoded. Access to any nonexisting physical memory returns NOP. The instruction pointer keeps increasing until it reaches 0FFFFh (top of IP), then it wraps around to 0000h. The data pointer is fully decoded. Access to any nonexisting physical memory returns a value of 0. If an instruction requests the data pointer to be increased, it keeps increasing until it reaches 0FFFFh (top of DP), then it wraps around to 0000h. If an instruction requests the data pointer to be decreased, it keeps decreasing until it reaches 0000h, then it wraps around to 0FFFFh. The last word in sector 1 (07FFh) is used as a security lock. When content of the security word[15:0] is equal to FFFFh, the memory is unsecured and program and erase operations are allowed. When security word[15:0] is any other value, all memory write operations are blocked by the hardware. CAUTION: Do not write any value other than FFFFh in memory location 07FFh (last word of the Flash memory). Any value other than FFFFh in this location PERMANENTLY secures the Flash memory and no further Flash write or erase operations are allowed. All erase/program operations are under the control of the Flash controller and assisted by the ROM code. Program Stack Automotive, Two-Channel Proximity and Touch Sensor The device does not support individual word programming. A whole page must be programmed at the same time. In attempts to write to an individual word, the data intended for the individual word is copied to the entire page. CAUTION: It is the user's responsibility to ensure that a Flash high-voltage operation (erase or write) is allowed to complete without external intervention. When an external intervention such as POR, or asserting the reset pin, is applied during a Flash high-voltage operation, the Flash operation is aborted. This can cause irreversible damage to the Flash and make the Flash inoperable. Instruction Set The device supports all the standard MAXQ20 instructions when executing from Flash and the utility ROM (Table 12). For a complete list of instructions and detailed descriptions, refer to the MAXQ Family Instruction Set Summary in the MAXQ Family User's Guide. MAX1441 Table 12. MAXQ Family Instruction Set Summary MNEMONIC AND src OR src XOR src CPL NEG SLA SLA2 SLA4 RL RLC SRA SRA2 SRA4 SR RR RRC MOVE C, Acc. MOVE C, #0 MOVE C, #1 CPL C MOVE Acc., C AND Acc. OR Acc. XOR Acc. MOVE dst., #1 MOVE dst., #0 MOVE C, src. ADD src ADDC src SUB src SUBB src DESCRIPTION Acc Acc AND src Acc Acc OR src Acc Acc XOR src Acc ~Acc Acc ~Acc + 1 Shift Acc left arithmetically Shift Acc left arithmetically twice Shift Acc left arithmetically four times Rotate Acc left (w/o C) Rotate Acc left (through C) Shift Acc right arithmetically Shift Acc right arithmetically twice Shift Acc right arithmetically four times Shift Acc right (0 msbit) Rotate Acc right (w/o C) Rotate Acc right (though C) C Acc. C0 C1 C ~C Acc. C C C AND Acc. C C OR Acc. C C XOR Acc. dst. 1 dst. 0 C src. Acc Acc + src Acc Acc + (src + C) Acc Acc - src Acc Acc - (src + C) 16-BIT INSTRUCTION STATUS BITS WORD AFFECTED f001 1010 ssss ssss f010 1010 ssss ssss f011 1010 ssss ssss 1000 1010 0001 1010 1000 1010 1001 1010 1000 1010 0010 1010 1000 1010 0011 1010 1000 1010 0110 1010 1000 1010 0100 1010 1000 1010 0101 1010 1000 1010 1111 1010 1000 1010 1110 1010 1000 1010 1011 1010 1000 1010 1010 1010 1000 1010 1100 1010 1000 1010 1101 1010 1110 1010 bbbb 1010 1101 1010 0000 1010 1101 1010 0001 1010 1101 1010 0010 1010 1111 1010 bbbb 1010 1001 1010 bbbb 1010 1010 1010 bbbb 1010 1011 1010 bbbb 1010 1ddd dddd 1bbb 0111 1ddd dddd 0bbb 0111 fbbb 0111 ssss ssss f100 1010 ssss ssss f110 1010 ssss ssss f101 1010 ssss ssss f111 1010 ssss ssss S, Z S, Z S, Z S, Z S, Z C, S, Z C, S, Z C, S, Z S C, S, Z C, Z C, Z C, Z C, S, Z S C, S, Z C C C C S, Z C C C C, S, E, Z C, S, E, Z C C, S, Z, OV C, S, Z, OV C, S, Z, OV C, S, Z, OV AP INC/DEC Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- -- -- -- -- Y Y Y Y NOTES 4 4 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 5 4 4 4 4 MATH BIT OPERATIONS LOGICAL OPERATIONS 33 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 12. MAXQ Family Instruction Set Summary (continued) MNEMONIC {L/S}JUMP src {L/S}JUMP C, src {L/S}JUMP NC, src {L/S}JUMP Z, src {L/S}JUMP NZ, src {L/S}JUMP E, src {L/S}JUMP NE, src {L/S}JUMP S, src {L/S}DJNZ LC[n], src {L/S}CALL src RET RET C RET NC RET Z RET NZ RET S RETI RETI C RETI NC RETI Z RETI NZ RETI S XCH (MAXQ20 only) XCHN MOVE dst, src PUSH src POP dst POPI dst CMP src NOP DESCRIPTION IP IP + src or src If C=1, IP (IP + src) or src If C=0, IP (IP + src) or src If Z=1, IP (IP + src) or src If Z=0, IP (IP + src) or src If E=1, IP (IP + src) or src If E=0, IP (IP + src) or src If S=1, IP (IP + src) or src If --LC[n] <> 0, IP (IP + src) or src @++SP IP+1; IP (IP+src) or src IP @SP-If C=1, IP @SP-If C=0, IP @SP-If Z=1, IP @SP-If Z=0, IP @SP-If S=1, IP @SP-IP @SP-- ; INS 0 If C=1, IP @SP-- ; INS 0 If C=0, IP @SP-- ; INS 0 If Z=1, IP @SP-- ; INS 0 If Z=0, IP @SP-- ; INS 0 If S=1, IP @SP-- ; INS 0 Swap Acc bytes Swap nibbles in each Acc byte dst src @++SP src dst @SP-dst @SP-- ; INS 0 E (Acc = src) No operation 16-BIT INSTRUCTION STATUS BITS WORD AFFECTED -- f000 1100 ssss ssss -- f010 1100 ssss ssss -- f110 1100 ssss ssss -- f001 1100 ssss ssss -- f101 1100 ssss ssss -- 0011 1100 ssss ssss -- 0111 1100 ssss ssss -- f100 1100 ssss ssss -- f10n 1101 ssss ssss -- f011 1101 ssss ssss -- 1000 1100 0000 1101 -- 1010 1100 0000 1101 -- 1110 1100 0000 1101 -- 1001 1100 0000 1101 -- 1101 1100 0000 1101 -- 1100 1100 0000 1101 -- 1000 1100 1000 1101 -- 1010 1100 1000 1101 -- 1110 1100 1000 1101 -- 1001 1100 1000 1101 -- 1101 1100 1000 1101 -- 1100 1100 1000 1101 1000 1010 1000 1010 1000 1010 0111 1010 fddd dddd ssss ssss f000 1101 ssss ssss 1ddd dddd 0000 1101 1ddd dddd 1000 1101 f111 1000 ssss ssss 1101 1010 0011 1010 S S C, S, Z, E -- C, S, Z, E C, S, Z, E E -- AP INC/DEC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Y Y (Note 8) -- -- -- -- -- NOTES 6 6 6 6 6 6 6 6 6 6, 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7, 8 7 7 7 -- -- Note 4: The active accumulator (Acc) is not allowed as the src in operations where it is the implicit destination. Note 5: Bit operation. Potentially affects C or E if the PSF register is the destination. Potentially affects S and/or Z if AP or APC is the destination. Note 6: The `{L/S}' prefix is optional. Note 7: Instructions that attempt to simultaneously push/pop the stack (e.g., PUSH @SP--, PUSH @SPI--, POP @++SP, POPI @++SP) or modify SP in a conflicting manner (e.g., MOVE SP, @SP--) are invalid. Note 8: Special cases: If `MOVE APC, Acc' sets the APC.CLR bit, AP is cleared, overriding any auto-inc/dec/modulo operation specified for AP. If `MOVE AP, Acc' causes an auto-inc/dec/modulo operation on AP, this overrides the specified data transfer (i.e., Acc is not transferred to AP). 34 DATA TRANSFER BRANCHING Automotive, Two-Channel Proximity and Touch Sensor Special System Functions The device supports interrupt through the Interrupt Vector (IV) register and the Interrupt Control (IC) register. The IV register allows the user program to set a preferred vector location to any program memory address. The IV register is fixed at 07FDh. Since the reset location can also be at 0000h, the user program must take care of any potential conflict between the reset and interrupt vector function. Interrupt sources can be classified into two categories: * Asynchronousinterrupt * Synchronousinterrupt The device supports the following asynchronous interrupts: * Externalinterrupts * Watchdoginterrupt * Timerinterrupts * AFEinterrupts All the other internal interrupts are synchronous interrupts. Synchronous internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle. Interrupt All functional units in the device are synchronized to the system clock that is generated from the 20MHz oscillator. The basic unit of time in the device is the system clock period. All storage logic blocks are triggered by the rising edge of the system clock. Clock Sources The internal clock circuitry generates the system clock from an internal 5MHz, which is derived from the 20MHz oscillator (Figure 4). Each time-code execution must start or restart (e.g., exiting stop mode), the following sequence occurs: 1) Remove clock gating of internal 5MHz. 2) Reset the warm-up counter. 3) Wait for Flash to power up (about 10Fs). 4) Allow the required warm-up delay of eight oscillator cycles of the 5MHz input. The only time 20MHz turns off is if the CPU is in stop mode and AFE is in standby mode or powered down (PD register = 6). During stop mode, if the AFE is in standby mode, the oscillator is periodically turned off and on to allow the AFE to sample inputs. This causes an interrupt to the CPU if an enabled threshold condition is met. Clock Generation MAX1441 Interrupt Sources POR STOP XDOG STARTUP TIMER XDOG_DONE FLASH CONTROLLER 20MHz OSCILLATOR /4 5MHz /4 1.25MHz STOP RESET POR SYSTEM CLOCK GENERATION SYSTEM CLOCK Figure 4. Clock Sources 35 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Table 13. Watchdog Timer Timeout Interval WD[1:0] 00 01 10 11 TIMEOUT COUNT 16384 32768 65536 131072 TIMEOUT (s) 0.5 1.0 2.0 4.0 Stop Mode The stop mode disables all circuits within the processor, unless explicitly stated otherwise. All microcontroller system clocks, timers, and serial communication are stopped and no processing is possible. However, the AFE can be left in the standby mode and remain functional. Once in stop mode, the CPU is in a static state. Its power consumption is mostly limited by the leakage current. Stop mode is invoked by setting the STOP bit to logic 1. The processor enters the stop mode on the instruction that sets the STOP bit. Entering the stop mode does not affect the setting of the clock control bits. This allows the system to return to its original operating frequency following the stop mode removal, except if the removal is caused by RST or a power loss, which resets the clock generation to its default condition. The processor can exit stop mode by: * Anyoftheexternalinterruptsthatareenabled. * ExternalresetusingtheRSTpin. * Timerinterrupt. * Watchdogtimeout. * AFEinterruptsthatareenabled. When the stop mode is removed, the device executes the following procedure: 1) Remove clock gating of internal 5MHz. 2) Reset the warm-up counter. 3) Wait for Flash to power up (about 10Fs). 4) Allow the required warm-up delay of eight oscillator cycles of the 5MHz input. 5) Resume normal operation. During stop mode, the following peripherals can be operational: * Timer(TMREN=1) * Watchdogtimer(WDCN.EWDI=1) * AFE The device has four ways of entering a reset state: * Power-onreset * Watchdogtimerreset * Externalreset * Internalsystemreset Watchdog Timer The watchdog timer is clocked by the internal 32kHz oscillator (Table 13). All timing reference for the watchdog is based on the 32kHz. In addition, the watchdog is disabled in debug mode and when SPE is set to 1. Clock to the watchdog is gated off in the conditions mentioned in the Clock Sources section. Startup Timer An independent startup timer (X-dog timer) functions: * Whenthedeviceisfirstpoweredup(POR) * Exisfromstopmode The X-dog counter is used to count eight oscillator cycles of the 5MHz after the power supply is stable. The power supply is stable after three-to-four 32kHz oscillator cycles. The AFE circuit is released at least one 32kHz oscillator cycle before the CPU to allow for the 5MHz clock startup to properly occur. The X-dog timer is active only for startup count; during normal operation, it is completely shut off. Idle Mode The device supports idle mode. Idle mode suspends the processor by holding the instruction pointer (IP) in a static state. No instructions are fetched and no processing occurs. Setting the IDLE bit in the SC register to logic 1 invokes the idle mode. The instruction that executes this step is the last instruction prior to freezing the program counter. Once in idle mode, all resources are preserved and all clocks remain active with the enabled peripherals. The power monitor continues to work, so the processor can exit the idle state using any of the interrupt sources that are enabled. The IDLE bit is cleared automatically once the idle state is exited, allowing the processor to execute the instruction that immediately follows the instruction that sets the IDLE bit. Resetting the processor also removes the idle mode. Reset places the processor in a reset state and clears the IDLE bit. 36 Reset Conditions Automotive, Two-Channel Proximity and Touch Sensor If the reset is caused by watchdog or external sources, the clock source (5MHz oscillator) remains running, but no program execution is allowed. When the reset source is external, the user must remove the reset stimulus. When power is applied to the device, the power-on delay removes the stimulus automatically. Power-On Reset Generation The device incorporates an internal voltage reference and comparator to monitor VDD and hold the device in reset if the supply is out of tolerance. Once VDD has risen above the VPOR threshold, the device generates a power-on reset, starts the internal 20MHz, and counts eight cycles of the derived 5MHz to ensure that Flash is powered up and the system clock source has had time to stabilize. The processor then exits the reset state automatically and starts executing the program at location 8000h. Software can determine that a POR has occurred by checking the power-on reset flag, POR in the WDCN register. Software should clear the POR flag after having read it. The POR is an asynchronous reset source. Watchdog Timer Reset The watchdog timer is a free-running timer with a programmable interval. The watchdog supervises the processor operation by requiring software to clear the timer counter before the timeout expires. If the timer is enabled and software fails to clear it before this interval expires, the device is placed into a reset state. The reset state maintains for about 90 system clock cycles. Once the reset is removed, the processor resumes execution at address 8000h. Software can determine if a reset is caused by a watchdog timeout by checking the watchdog timer reset flag, WTRF in the WDCN register. This flag is cleared by software only. External Reset If the RESET input is taken to logic 0, the device is forced into a reset state. An external reset is accomplished by holding the RESET pin low at least four clock cycles while the internal 5MHz clock is running. Once the reset state is invoked, it is maintained as long as RESET is pulled to logic 0. When the reset state is removed, the processor exits the reset state within four clock cycles and begin execution at address 8000h. If a reset state is applied while the processor is in the stop mode, the reset causes the processor to exit the stop mode and forces the program counter to 8000h. The reset delay is four clock cycles. The RESET is a bidirectional I/O. If a reset is caused by a watchdog timer reset or an internal system reset, an output reset pulse is also generated at the RESET pin. This reset pulse is asserted as long as a reset source is asserted and may not be able to drive the reset signal out if the RESET pin is connected to an RC reset circuitry. Connecting the RESET pin to a capacitor would not affect the internal reset condition. Internal System Reset An internal system reset can occur in system programming mode when the ROD bit is set to logic 1 while the SPE bit is 1. MAX1441 Timer The device has implemented an 8-bit timer with an 11-bit prescaler. The operation of the timer is configurable using the Timer Control register (TCON), Timer Frequency register (TFRQ), and the Timer Counter register (TCNT). The timer is enabled by setting the Timer Enable Bit (TCON.TMREN) to 1. Once enabled, the timer starts counting from the initial TCNT value up to the TFRQ limit. When TCNT = TFRQ, the timer interrupt flag (TMRIF) is set to 1. This can cause an interrupt to the CPU if the timer interrupt is enabled (TMRIE = 1). Once the frequency limit is reached, TCNT is reset to 0 and continue to count up again. The timer has two clock sources: system clock and the 32kHz clock. The selection is made using the Timer Clock Select (TCLK) bit. Due to different clock domains, when running off the 32kHz clock, reading of the TCNT register is only valid when the Timer Valid Flag (TVALID) is set to 1. When running the system clock, there is no restriction on running from TCLK. In addition, a write to TRMEN when running off the 32kHz clock can be delayed due to synchronization between the two domains. To increase the period between subsequent interrupts, an 11-bit prescaler is provided to prescale the input clock from 1 to 2048. If the timer is enabled and running off the 32kHz clock source prior to the stop mode entry, the timer continues to run and invoke a stop mode exit if the interrupt is enabled. 37 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 I/O Ports The device implements an I/O port that is slightly different from those found in other MAXQ products. The I/O port is still governed by the PI0, PO0, and PD0 registers. When a PD0 register is cleared to 0, the port pin is operating as input and the pin is high impedance. The PI register contains the input value. PI is read only. PI may not always immediately equal PO due to capacitance at the output. When a PD0 bit is set to 1, the output is enabled and the port pin output data corresponds to the PO value. In addition, P0.5 and P0.6 can ONLY be used as opendrain outputs. To use P0.5 and P0.6, clear PO bit to 0 and drive PD bit with inverted data. When used as inputs, do not leave the port unconnected. Program unused port pins as outputs. The external interrupt flag (EIF) is set to 1 when either a rising or falling edge is detected on a port pin regardless of its PD0 value. An interrupt is generated if it is enabled (EIE = 1). At power-up, weak pullups are enabled on pin P0.[4:0]. To disable a pullup, clear the associated bit in the PO0 register. The external interrupts are asynchronous. In the discussion that follows, priority only has meaning when two peripherals are both configured to drive outputs at the same time. Then one of the named peripheral's output has priority over the other, thus making the other's output disabled. Note that the lower priority peripheral can still be running and trying to output value onto the pad. However, since it has lower priority, its output is not driven onto the pad. For inputs, all peripherals have equal priority--even though the inputs may not be desirable. This means that if two input peripherals sharing the same pin are enabled, both of them receive the same input concurrently. When a pin operates as input (whether it is a GPIO or special-function input), its behavior is governed by PO0 and PD0. Anytime a pin behaves as an output (because one of its special functions is configured as output), PO0 and PD0 are no longer used. Port 0 supports the following functions: JTAG and GPIO. All special functions have priority over GPIO. The following apply when port pins are multiplexed with the JTAG function: * The Special-Function Enable (SF Enable) signal for these JTAG pins must be active during reset so that the JTAG port is accessible during this time. SF enable is controlled by the TAP register bit, which is set to 1 on all resets. * TheSpecial-FunctionInput,whendisabled,shouldbe gated high for TMS. This disables the JTAG interface and forces the TAP into the Test-Logic-Reset state if the TCK pin has been toggled for more than five times. * The TDO Special-Function Enable requires not only that TAP = 1, but also that the TAP be in the Shift-IR or Shift-DR state. The debug engine already produces a control signal (TDONZ) to denote when the TAP is in a shift state. JTAG Pin Special Function System Operating Modes Following each system reset, the device automatically activates the utility ROM at 8000h. The reset vector in the utility ROM determines whether the program flow is to start in the user mode or the ROM bootstrap mode. The factor that determines which program is executed is the System Programming Enable (SPE) bit in the ICDF register. The SPE can be set/cleared with the debug mode command using the TAP interface. The device supports various modes of system operations. Normally, the device is running in user mode to support user applications. The ROM bootstrap loader mode is used for initializing memory and system configuration. The debug mode is intended to provide real-time in-circuit debugging/emulation. The debug mode is supported through a test access port (TAP) and the TAP controller, which is compatible to the JTAG standard. The TAP and the TAP controller are enabled after any reset, but remain inactive until a valid command is entered into the instruction register so as not to disrupt normal user-mode operation. If the TAP is not used, or the TAP interface pins are needed to serve another purpose, the TAP can be disabled by clearing the TAP enable (TAP) bit located in the SC system register. Depending upon the mode desired, the instruction register should be loaded with the associated "debug" or "insystem programming" instruction. The method for loading the instruction register is described in the subsequent sections. These modes can be established anytime the digital supply voltage is above the POR threshold (e.g., during system reset both are acceptable). Peripheral Prioritization 38 Automotive, Two-Channel Proximity and Touch Sensor The device supports a TAP and TAP controller for communication with a bus master that can be either an automatic test equipment or a component that interfaces to a higher level test bus as part of a complete system. The communication operates across a 4-wire serial interface from a dedicated TAP, which is compatible to the JTAG IEEEM Standard 1149. The TAP is a generalpurpose port, which allows access to many debug and test functions built into the core. For detailed information on the TAP and TAP controller, refer to IEEE Standard 1149.1 IEEE Standard Test Access Port and Boundary-Scan Architecture. Bootstrap Loader Mode Internal nonvolatile memory can be initialized by the bootstrap loader in bootstrap loader mode. The bootstrap loader mode is enabled by an external host device using the TAP in the system programming instruction. The system programming function is supported using the system programming buffer (SPB): 1) SPB.0-System programming enable (SPE) When it is set, the bootstrap loader program is activated to perform a bootstrap loader function. When it is cleared, the reset vector forces the IP to 8000h and starts normal user-program execution. 2) SPB.2:1-Programming source select (PSS[1:0]) These bits allow the host to select programming interface sources: PSS1 0 0 1 1 PSS0 0 1 0 1 PROGRAMMING SOURCE JTAG Reserved Reserved Reserved JTAG Port Password-Protected Access Some applications require preventive measures to protect against simple access and viewing of program code memory. To address this need for code protection, the device grants full access to in-system programming or in-circuit debugging utilities only after a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. Note that using these memory locations for a password does not exclude their usage for general code space if a unique password is not needed. Also, if addresses 0010h to 001Fh contain all zeros or all FFFFs, the password function is effectively disabled and a password is not needed to gain access. A single password lock bit (PWL) is implemented in the SC register. When the PWL is set to 1, a password is required to access the ROM loader utilities, which support read/write accessing of internal memory and debug functions. When PWL is cleared to 0, these utilities are fully accessible through the utility ROM without a password. The PWL bit defaults to 1 by a POR. To access the ROM utilities, a correct password is needed; otherwise, access of ROM utilities is denied. Once the correct password has been supplied by the user, the ROM utility clears the password lock. The PWL remains clear until one of the following occurs: * Apower-onreset OR * Settologic1byusersoftware. Entering Password A password can be entered: * Using the interface established by the PSS1 and PSS0 bits in system programming when the SPE bit is set to logic 1; the ROM loader must establish a suitable protocol for that interface to recognize the multibyte password. OR * ThroughtheTAPinterfacedirectlyindebugmodeor test mode by issuing a password-unlock command; this command requires 32 follow-on transfer cycles, each containing a byte value compared with the password. MAX1441 User applications are executed in user mode. In user mode, the processor can execute program routines in any memory segments. Normally, data is loaded and stored from/to the data memory. The device contains three memory segments among the program and the data spaces: * Programsegment * Datasegment * UtilityROMsegment User Mode IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. 39 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Applications Information For best performance, use PCBs. Ensure to separate digital and analog signal lines from each other. Do not run analog and digital signals parallel to one another (especially clock signals) or do not run digital lines underneath the IC package. High-frequency noise in the power-supply lines can affect performance. Bypass the VAA and VDD supplies with 0.47FF capacitors close to VAA and VDD. Bypass the VBATT supply with a 0.1FF capacitor close to the VDD pin. Minimize capacitor lead lengths for best supply-noise rejection. Refer to the MAX1441 Evaluation Kit for an example of proper layout. Chip Information PROCESS: BiCMOS Layout, Grounding, and Bypassing Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 90-0116 20 TSSOP U20M+2 21-0066 40 Automotive, Two-Channel Proximity and Touch Sensor MAX1441 Revision History REVISION NUMBER 0 REVISION DATE 6/10 Initial release DESCRIPTION PAGES CHANGED -- Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 41 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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